Programmable Signal Processor Register Sharing for Parallel Throughput

The shift register file is designed to serve multiple functions: it acts as both a data storage structure and a data transfer mechanism between parallel execution circuits. The same register file structure enables both data sharing and synchronization without requiring separate interface circuits, thus improving adaptability while maintaining circuit simplicity.

The parallel execution circuits automatically share data through the common register file using shift operations controlled by a global shift signal. Each execution circuit can directly read from and write to the register file without needing dedicated interface circuits or control programs, enabling self-service data transfer that reduces overall circuit complexity.

A global shift signal is periodically generated to synchronize data transfer between parallel execution circuits at predetermined timing. This periodic synchronization mechanism coordinates the BUSY states of multiple DSPs without requiring complex real-time negotiation, enabling high throughput while maintaining manageable coordination complexity through regular, predictable operation cycles.

Multiple execution circuits share a common register file and synchronization mechanism, merging the data storage and coordination functions into a unified structure. This consolidation allows parallel DSPs to operate simultaneously with improved throughput while reducing coordination complexity by eliminating the need for separate interface and control circuitry for each DSP pair.