Programmable Test Compression Architecture Input Output Shift Register
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current test compression architectures (TCAs) face challenges in efficiently accessing and testing electrical devices using either high-cost parallel testers or low-cost serial testers, particularly in daisy-chain arrangements, leading to increased test time and the need for customized test patterns.
Innovation Solution
The implementation of a programmable access TCA (PAT) that allows selective access using either parallel or serial interfaces, incorporating multiplexers, input/output shift registers, and additional circuitry to enable testing with both high-cost parallel and low-cost serial testers, including JTAG controllers, thereby standardizing test patterns across different configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a test compression architecture is accessed using a parallel interface, then testing efficiency is improved, but tester cost increases
Solution Approach 1:
The test compression architecture is designed with dual interface capability, allowing the same architecture to be accessed through both parallel and serial interfaces. The multiplexer dynamically routes between parallel input/output buses and serial input/output interfaces, enabling a single architecture to serve both high-performance parallel testing and cost-effective serial testing scenarios.
2Ease of manufacture
If a test compression architecture is accessed using a serial interface, then tester cost is reduced, but test time increases
Solution Approach 1:
The system dynamically adapts its interface mode based on operational requirements. The multiplexer can switch between serial and parallel modes, allowing the system to use serial interface for cost-sensitive applications and parallel interface for time-critical testing scenarios, optimizing the trade-off between cost and test time.
3Measurement precision
If customized test patterns are used for different configurations, then testing accuracy is improved, but complexity increases
Solution Approach 1:
A single standardized test pattern set is designed to work across both parallel and serial interface configurations. The multiplexer and control logic handle the adaptation to different interface types, eliminating the need for separate customized test patterns for each configuration while maintaining testing accuracy.
4Speed
If parallel input/output buses are used, then data transmission speed is improved, but device complexity increases
Solution Approach 1:
The multiplexer combines the parallel and serial interface paths into a single unified structure. By sharing common resources such as the test compression architecture, scan paths, and control logic between parallel and serial modes, the overall device complexity is reduced compared to having completely separate interface systems.
Data Source
AI summary
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.