Programmable Voltage Regulation for Processor Voltage Droop
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Solution Overview
Problem
CMOS integrated circuits face power consumption issues due to voltage droop during sudden increases in load, leading to potential circuit failure, as existing power management mechanisms are inadequate in responding quickly and accurately to voltage changes.
Innovation Solution
A data processing system with an adaptive digital frequency locked loop (DFLL) and a voltage regulator that automatically adjusts the clock frequency and power supply voltage in response to power supply current exceeding a designated limit, using a steep voltage-current relationship to maintain stable operation during voltage droop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power supply voltage is reduced to lower power consumption, then energy efficiency improves, but voltage droop during sudden load increases causes circuit failure
Solution Approach 1:
The patent implements dynamic voltage and frequency adjustment by monitoring power supply current in real-time. When current exceeds the EDC limit, the system automatically reduces clock frequency and adjusts voltage according to the programmed load line slope, creating a dynamic response to changing load conditions that prevents voltage droop while maintaining energy efficiency during normal operation
Solution Approach 2:
The system uses feedback from power supply current monitoring to trigger protective actions. The current monitor continuously measures power supply current and provides feedback to the control logic, which then adjusts frequency and voltage based on the measured current level, ensuring the system operates within safe voltage margins while maximizing performance
2Device complexity
If existing power management mechanisms are used to respond to voltage changes, then system complexity is maintained, but response speed is insufficient to prevent voltage droop circuit failure
Solution Approach 1:
The patent combines multiple functions into a unified power management approach: current monitoring, frequency control, and voltage regulation are integrated into a single coordinated system. The load line programming mechanism unifies the control of both frequency and voltage under one current-threshold-based framework, simplifying the overall system while enabling fast response through centralized control logic
3Reliability
If clock frequency is reduced to prevent voltage droop circuit failure, then voltage stability improves, but processing performance deteriorates
Solution Approach 1:
The system dynamically adjusts clock frequency based on real-time power supply current conditions. During normal operation below the EDC limit, the processor runs at maximum frequency for optimal performance. When current exceeds the limit indicating impending voltage droop, the frequency is reduced only as necessary to maintain stable operation, allowing the system to achieve maximum productivity when safe and maintain reliability when needed
Solution Approach 2:
The patent changes the operating parameters (frequency and voltage) based on the measured power supply current. By programming the load line slope that relates current to frequency and voltage adjustments, the system optimizes the parameter changes to maintain processing performance while preventing voltage droop, rather than using fixed conservative settings
Data Source
AI summary
A data processor includes at least one power supply voltage terminal for receiving a power supply voltage and a power supply current, a data processing circuit, a register, and a port controller. The data processing circuit is coupled to the at least one power supply voltage terminal and operates using the power supply voltage. The register stores a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship for an external voltage regulator when the power supply current exceeds the EDC limit. The port controller is coupled to the register and to an output port. The data processing circuit is operative to cause the port controller to output the nominal value of the power supply voltage, the EDC limit, and the EDC slope over the output port for use by the external voltage regulator.