PROM Configuration Memory Updates via Direct JTAG Addressing
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Solution Overview
Problem
Existing programmable logic devices (PLDs) require time-consuming and error-prone processes for updating configuration files, as they typically necessitate erasing all data in external PROMs and reprogramming with new configuration files, which is inconvenient and infeasible in deployed applications.
Innovation Solution
A system that allows direct access to individual storage locations in a memory storing configuration information, enabling selected data updates without erasing all contents or reprogramming the memory, using a controller to mark data as stale and valid, thereby allowing incremental updates and reducing configuration errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chip erase function is used to update PROM data, then new data can be programmed, but all existing data is lost and reprogramming is required
Solution Approach 1:
The patent divides the configuration data into multiple segments or blocks that can be independently accessed and updated. Instead of treating the entire PROM content as a single unit requiring full erase/reprogram, the system allows selective modification of individual data blocks through direct memory addressing, thereby reducing configuration time while maintaining data update capability
Solution Approach 2:
The patent implements a preliminary action by pre-organizing configuration data into addressable blocks with associated status bits that indicate validity. This preliminary structuring enables subsequent selective updates without requiring full erasure, as the system can identify and modify only the specific blocks that need updating while preserving others
2Adaptability or versatility
If chip erase function is used to update PROM data, then new data can be programmed, but the process becomes error-prone and inconvenient
Solution Approach 1:
The patent applies preliminary action by pre-structuring configuration data into addressable blocks with validity status bits before deployment. This preliminary organization enables reliable selective updates through direct addressing, eliminating the error-prone full erase/reprogram process while maintaining configuration integrity through controlled data modification
Solution Approach 2:
The patent implements feedback mechanisms through status bits associated with each data block that indicate whether the data is valid or stale. This feedback system allows the controller to verify data integrity during selective updates, ensuring that only valid data is used for configuration and preventing errors that would occur with blind full reprogramming
3Adaptability or versatility
If full PROM reprogramming is performed, then configuration can be updated, but previous data versions are lost
Solution Approach 1:
The patent segments configuration data into independently addressable blocks, each with its own validity status bit. This segmentation allows selective updating of individual blocks while preserving others, enabling retention of previous data versions in unchanged blocks and providing the option to revert if needed, thus preventing complete information loss
Solution Approach 2:
The patent implements a discard and recover mechanism where data blocks are marked as stale (discarded) rather than physically erased when updated. The original data remains in memory but is flagged as invalid, allowing recovery of previous versions by simply clearing the stale bit if the new data proves erroneous, thus preventing permanent information loss
Data Source
AI summary
Individual storage locations in a PROM that stores a configuration file for a PLD may be directly addressed so that selected portions of the data stored therein may be replaced or updated with new data without having to erase all the contents of the PROM, reprogram the PROM with a new configuration file, and/or reconfigure the FPGA with the new configuration file. For some embodiments, a PROM includes a JTAG-compatible interface that is coupled to a JTAG-compatible test circuit provided within the PLD, and circuit within the PLD is configured to directly address individual storage locations in the PROM via the PROM's JTAG interface using well-known JTAG commands.