Proxy Interface for Direct DMA Between NIC and SSD
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Solution Overview
Problem
Current bus architectures, such as PCIe, require NICs and SSDs to transfer data through host memory, introducing latency and consuming bandwidth and CPU cycles, as both devices are conventionally defined as bus masters and cannot directly transfer data via the bus.
Innovation Solution
An interface device with two proxy interfaces and a buffer memory is used to facilitate direct memory access (DMA) transactions between NICs and SSDs, allowing data transfer without involving the host memory, while maintaining bus-master functionality, by emulating host memory behavior and using multiplexing logic to convey transactions between the SSD and the bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred through host memory using conventional bus architectures, then data transfer between NICs and SSDs is enabled, but latency increases and bandwidth is consumed
Solution Approach 1:
The patent introduces a proxy interface as an intermediary component between the NIC and SSD. This proxy acts as a mediator that enables direct DMA transactions between the two devices by handling address translation and transaction routing, eliminating the need for data to traverse host memory while maintaining compatibility with existing bus architectures.
Solution Approach 2:
The patent segments the data transfer path by creating separate transaction channels: one for NIC-initiated DMA transactions and another for SSD-initiated DMA transactions. Each proxy interface handles transactions from its respective device independently, allowing parallel operation and reducing contention on the shared bus while avoiding host memory involvement.
2Adaptability or versatility
If data is transferred through host memory, then standard bus-master functionality is maintained, but bandwidth consumption increases and CPU cycles are consumed
Solution Approach 1:
The proxy interface serves as an intermediary that preserves the bus-master functionality of both NIC and SSD by translating their DMA transactions into appropriate bus operations. It handles address space mapping and transaction formatting, allowing both devices to operate as bus masters simultaneously without requiring data to pass through host memory, thereby reducing bandwidth consumption and power usage.
3Productivity
If direct DMA transactions between NICs and SSDs are enabled, then latency is reduced and bandwidth is saved, but device complexity increases
Solution Approach 1:
The proxy interface introduces controlled complexity by centralizing the intelligence needed for direct DMA operations in a single intermediary component. This approach manages address translation, transaction routing, and buffer management in one location, which simplifies the overall system architecture compared to distributing this functionality across multiple devices. The added complexity is localized and manageable, enabling significant productivity gains through reduced latency and improved transfer efficiency.
4Speed
If host memory is bypassed for data transfer, then transfer speed improves, but compatibility with existing host buses may be compromised
Solution Approach 1:
The proxy interface maintains host bus compatibility by acting as an intermediary that translates direct DMA transactions into standard bus protocols. It handles address space mapping and transaction formatting to ensure compatibility with existing PCIe and other host bus standards, while simultaneously enabling faster direct transfers between NIC and SSD by bypassing host memory for the actual data movement.
Data Source
AI summary
An interface device includes a first proxy interface configured to carry out first direct memory access (DMA) transactions initiated by an input/output (I/O) device and a second proxy interface configured to carry out second DMA transactions initiated by a storage drive. A buffer memory is coupled between the first and second proxy interfaces and configured to temporarily hold data transferred in the first and second DMA transactions. Control logic is configured to invoke the second DMA transactions in response to the first DMA transactions so as to cause the data to be transferred via the buffer between the I/O device and the storage drive.