Pseudo-Reduced 4CPP SRAM Layout for Shorter Bit Line Routing
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Solution Overview
Problem
Existing SRAM devices with 4CPP architecture face high bit line capacitance due to the alternately arranged even-numbered and odd-numbered rows along the lengthwise direction of bit lines, leading to undesirably long bit line routing and increased capacitive loading.
Innovation Solution
The memory array is designed with a pseudo-reduced 4CPP architecture where even-numbered and odd-numbered rows are alternately arranged along the word lines, reducing the length of bit lines by incorporating multiple word lines into each word line set, thereby decreasing capacitive loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If even-numbered and odd-numbered rows are alternately arranged along the bit lines in 4CPP architecture, then the memory array can be formed with standard architecture, but the bit line routing length increases and bit line capacitance increases
Solution Approach 1:
The patent changes the arrangement dimension from bit line direction to word line direction. Even-numbered and odd-numbered rows are alternately arranged along the word lines instead of bit lines, which reduces bit line routing length while maintaining manufacturability of the memory array
2Device complexity
If even-numbered and odd-numbered rows are alternately arranged along the bit lines, then the memory array structure is simplified, but the capacitive loading increases
Solution Approach 1:
The patent resolves the capacitive loading issue by changing the arrangement orientation to word line direction. This dimensional change reduces bit line length and thus capacitive loading, while the alternating row arrangement along word lines maintains structural simplicity
3Length of stationary object
If bit line routing length is reduced by changing row arrangement, then bit line capacitance decreases, but the row arrangement becomes more complex
Solution Approach 1:
The patent applies asymmetric arrangement where even-numbered and odd-numbered rows are alternately positioned along word lines. This asymmetric pattern optimizes bit line routing length and reduces capacitance while maintaining reasonable structural organization
Data Source
AI summary
A semiconductor device includes a first memory cell in a 4CPP architecture; a second memory cell formed in the 4CPP architecture and physically disposed next to the first memory cell along a first lateral direction; a first word line extending along the first lateral direction and operatively coupled to the first memory cell; a second word line extending along the first lateral direction and operatively coupled to the first memory cell; a third word line extending along the first lateral direction and operatively coupled to the second memory cell; a fourth word line extending along the first lateral direction and operatively coupled to the second memory cell; a first bit line extending along a second lateral direction perpendicular to the first lateral direction and operatively coupled to the first memory cell; and a second bit line extending along the second lateral direction and operatively coupled to the second memory cell.