Pseudo-DRAM PUF Circuit for Fast Operation in Extreme Temperatures
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Solution Overview
Problem
Leakage-based PUF generators, particularly those using DRAM, face reliability and speed issues due to temperature-dependent sub-threshold currents, making them unsuitable for wide-range temperature operations.
Innovation Solution
A CMOS pseudo-DRAM PUF generator with a plurality of bit cells, each comprising two inverters and a floating capacitor, utilizes inherent process variations to generate a unique PUF signature by monitoring transient discharge behaviors across dynamic nodes, allowing operation under extreme conditions with fast response times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If leakage-based PUF generators use sub-threshold current for operation, then cost effectiveness and reliability are improved, but response speed and reliability become sensitive to temperature variations
Solution Approach 1:
The patent changes the dominant leakage mechanism from sub-threshold current (temperature-dependent) to gate oxide leakage current (temperature-independent) by adjusting transistor operating parameters and bias conditions. This allows the PUF generator to maintain reliable operation across wide temperature ranges by shifting to a different physical mechanism that is less sensitive to temperature variations.
Solution Approach 2:
The patent substitutes the sub-threshold current mechanism with gate oxide leakage current mechanism. This replacement transitions from a temperature-sensitive transport phenomenon to a temperature-insensitive tunneling phenomenon, thereby improving temperature adaptability while maintaining reliability.
2Use of energy by moving object
If leakage-based PUF generators operate at low temperatures, then power consumption is reduced, but response time increases due to dominant sub-threshold current
Solution Approach 1:
The patent modifies operating parameters to induce gate oxide leakage dominance over sub-threshold current. By changing the leakage mechanism to one that is not strongly temperature-dependent, the system maintains fast response times even at low temperatures where power consumption is reduced, breaking the traditional trade-off between energy efficiency and speed.
3Ease of manufacture
If traditional DRAM PUF generators are used, then cost effectiveness is improved, but operational reliability under extreme conditions deteriorates
Solution Approach 1:
The patent modifies the operating parameters of standard DRAM-based PUF structures to shift the dominant leakage mechanism. This allows existing manufacturing processes to be used (maintaining cost effectiveness) while achieving reliable operation under extreme conditions through the temperature-insensitive gate oxide leakage mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable and fast PUF signature generation across a wide range of temperatures, enhancing the operational stability and efficiency of leakage-based PUF devices.
Implementation Method 1
A CMOS pseudo-DRAM PUF generator with a plurality of bit cells, each comprising two inverters and a floating capacitor
Implementation Method 2
when a leakage current of such device is dominated by a temperature-dependent sub-threshold current
Data Source
AI summary
Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.