Pseudo Page Mode MRAM Architecture Using MTJ and Bistable Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices, such as DRAM and SRAM, are volatile and cannot retain data without a power supply, while non-volatile memories like flash suffer from slow programming time and higher testing costs. Additionally, existing non-volatile memory devices face challenges in achieving balanced current requirements for writing '0' and '1' states in MRAM cells.
Innovation Solution
A non-volatile memory array architecture utilizing magnetic tunnel junctions (MTJs) coupled with transistors and bistable regenerative circuits, where each memory cell has two current-carrying terminals connected to common data lines and a control terminal to a word line, enabling efficient data storage and retrieval, and allowing for page mode or burst mode operations, emulating DDR DRAM operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile memory devices are used, then data retention is improved, but programming time increases and testing costs increase
Solution Approach 1:
The patent replaces the conventional charge-based storage mechanism with a magnetic storage mechanism using magnetic tunnel junctions (MTJs). The MTJ utilizes spin-polarized electron transport and magnetization switching to store data, substituting electrical charge storage with magnetic state storage. This fundamental mechanism substitution enables non-volatile data retention while achieving faster write speeds comparable to volatile memory, directly resolving the contradiction between data retention and programming time.
Solution Approach 2:
The patent employs spin-transfer torque (STT) to change the magnetization state of the free layer in the MTJ by applying a current pulse. By controlling the current direction and magnitude, the magnetization can be switched between parallel and anti-parallel states, enabling fast and reliable data writing. This parameter control mechanism allows for rapid programming while maintaining non-volatile storage, addressing both the reliability and productivity concerns.
2Reliability
If conventional non-volatile memory devices are used, then data retention is improved, but testing costs increase
Solution Approach 1:
The patent implements a dual-mode memory architecture where the same MTJ-based cell can operate in both volatile and non-volatile modes. The bistable regenerative circuit can function as a latch for volatile operation or as a non-volatile storage element when combined with the MTJ. This multi-functionality allows the memory to serve multiple purposes, reducing the need for separate testing protocols and lowering testing costs while maintaining data retention capabilities.
3Reliability
If MTJ structures are used for non-volatile storage, then data retention is improved, but current balance for writing '0' and '1' states deteriorates
Solution Approach 1:
The patent acknowledges and utilizes the asymmetric switching characteristics of MTJs, where the current required to switch from parallel to anti-parallel state differs from the current required to switch from anti-parallel to parallel state. The write driver circuit is designed with asymmetric current control, providing different current levels and pulse durations depending on the desired write state. This asymmetric control compensates for the inherent MTJ asymmetry, achieving balanced and reliable writing of both '0' and '1' states while maintaining non-volatile storage functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides the cost benefits of DRAM, the fast read and write performance of SRAM, and the non-volatility of flash memory, while overcoming the limitations of slow programming times and high testing costs, enabling efficient data retention and operation in MRAM devices.
Implementation Method 1
the voltage difference causes spin polarized electrons flowing from free layer 16 to reference layer 12 to transfer their angular momentum and change the magnetization direction of free layer 16
Implementation Method 2
When free layer 16 and reference layer 12 have the same magnetization direction (parallel state), MTJ 10 has a relatively low resistance. Conversely, when free layer 16 and reference layer 12 have the opposite magnetization direction (anti-parallel state), MTJ 10 has a relatively high resistance.
Data Source
AI summary
A non-volatile memory array includes a plurality of word-lines and a plurality of columns. One of the columns further includes a bistable regenerative circuit coupled to a first, a second, a third, and a fourth signal lines. The column also includes a non-volatile memory cell having current carrying terminals coupled to the first and second signal lines and a control terminal coupled to one of the plurality of word-lines. The column further includes a first transistor and a second transistor. The first transistor is coupled to the first terminal of the bistable regenerative circuit, and to a fifth signal line. The second transistor has a first current carrying terminal coupled to the second terminal of the bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line. The gate terminals of the first and second transistors are coupled to a seventh signal line.