Pseudo Pass-Gate Ring Oscillator for PVT Phase Realignment
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Solution Overview
Problem
Current ring oscillators in phase-locked loop (PLL) circuits face challenges in reducing phase noise and frequency variations due to process, voltage, and temperature (PVT) variations, which affect their performance in ASICs such as network controllers and graphics processors.
Innovation Solution
The proposed solution involves a ring oscillator design with a controlling circuit and a delay chain that includes pseudo pass-gate inverters and dummy transistors, utilizing a realignment signal to enable or disable the pseudo pass-gate inverter and adjust the waveform, thereby aligning the phase without additional electronic components like multiplexers, ensuring low power consumption and easy integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ring oscillator design is used, then circuit simplicity is maintained, but phase noise and frequency variations increase due to PVT variations
Solution Approach 1:
The ring oscillator is divided into multiple delay cells, each with independent PMOS and NMOS transistors that can be individually controlled. This segmentation allows selective disabling of specific transistor pairs through the realignment signal, enabling phase adjustment without redesigning the entire oscillator structure.
Solution Approach 2:
The circuit introduces dynamic control capability through the realignment signal that can selectively enable or disable specific transistor pairs (PMOS and NMOS) in the delay chain. This dynamic control allows the oscillator to adapt its phase and frequency characteristics in response to PVT variations while maintaining a relatively simple static structure.
2Reliability
If additional electronic components like multiplexers are added to align phase, then phase alignment capability is improved, but power consumption and device complexity increase
Solution Approach 1:
The existing PMOS and NMOS transistors in the delay chain are made multi-functional by adding control capabilities. These transistors not only perform their standard switching function but also serve as phase adjustment elements when controlled by the realignment signal, eliminating the need for separate phase adjustment components.
Solution Approach 2:
The ring oscillator uses its own existing transistor structures (PMOS and NMOS pairs) to perform the phase alignment function that would traditionally require external components. The circuit realigns its own phase using internal resources, avoiding additional power-consuming components.
3Reliability
If additional electronic components are added to adjust waveform phase, then phase alignment is achieved, but integration cost and device complexity increase
Solution Approach 1:
The phase adjustment function is merged with the existing delay cell structure. The PMOS and NMOS transistors that form the basic oscillation units are also used as phase control elements, combining two functions (oscillation and phase adjustment) into a single integrated structure that reduces manufacturing complexity.
Solution Approach 2:
The delay chain transistors serve dual purposes: maintaining oscillation and enabling phase alignment. This multi-functionality reduces the total component count and simplifies the manufacturing process, as no separate phase adjustment components need to be fabricated.
Data Source
AI summary
A ring oscillator is provided. The ring oscillator includes a pseudo pass-gate inverter, a third transistor, a fourth transistor and a delay chain. The pseudo pass-gate inverter includes a first transistor and a second transistor in series. The third transistor is connected in series with the pseudo pass-gate inverter. The drain of the fourth transistor is connected to an output of the pseudo pass-gate inverter. The gate of the fourth transistor is connected to the gate of the third transistor to receive the realignment signal. The delay chain includes a plurality of delay cells. An input of the delay chain is connected to the output of the pseudo pass-gate inverter. When the realignment signal is in a realignment state, the third transistor is turned off, the fourth transistor is turned on.