Pseudo-Split DDR6 Memory Die Access Without Rank-Switching Penalty
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Solution Overview
Problem
Existing DDR5 architectures face increased design complexity, fabrication complexity, and cost due to extensive wiring between different ranks on a DIMM circuit board, along with a penalty in idle cycles during rank switching and the need for CA data interleaving, which reduces bandwidth.
Innovation Solution
The introduction of pseudo-split dies within a physical DDR6 DIMM die package, where each pseudo-split die has its own interface circuitry and operates independently, allowing data streams to exit the die separately and then be multiplexed, reducing the need for extensive wiring and eliminating the rank-switching penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If extensive wiring is used to connect different ranks on a DIMM circuit board, then data transfer capability is improved, but design complexity and fabrication complexity increase
Solution Approach 1:
The memory die is divided into multiple independent pseudo-split dies (first pseudo-split die and second pseudo-split die), each with its own interface circuitry. This segmentation eliminates the need for extensive wiring between ranks, as each pseudo-split die can be accessed independently through separate command and address channels, thereby reducing design complexity while maintaining data transfer capability.
Solution Approach 2:
The patent introduces a new architectural dimension by implementing pseudo-split dies within a single physical die package, allowing parallel access paths that were previously achieved only through separate physical dies. This dimensional reorganization enables independent interface circuitry for each pseudo-split die, reducing the need for complex inter-rank wiring on the DIMM circuit board.
2Productivity
If extensive wiring is used to connect different ranks on a DIMM circuit board, then data transfer capability is improved, but fabrication complexity and cost increase
Solution Approach 1:
By segmenting the memory die into independent pseudo-split dies with separate interface circuitry, the patent eliminates the need for complex inter-rank wiring. This segmentation allows each pseudo-split die to be fabricated and tested independently, simplifying the manufacturing process and reducing costs while maintaining high data transfer capability through parallel access.
3Adaptability or versatility
If rank switching is implemented, then memory access flexibility is improved, but idle cycles occur reducing performance
Solution Approach 1:
The memory die is segmented into multiple pseudo-split dies that can be accessed simultaneously through separate command and address channels. This eliminates the need for rank switching, as each pseudo-split die operates independently without requiring idle cycles for switching, thereby maintaining memory access flexibility while improving performance.
Solution Approach 2:
By implementing independent interface circuitry for each pseudo-split die, the patent enables continuous data access without interruption for rank switching. The separate command and address channels allow simultaneous operations on different pseudo-split dies, eliminating idle cycles and maintaining continuous useful action, thus improving overall performance while preserving access flexibility.
4Productivity
If CA data interleaving is used, then bandwidth utilization is improved, but complexity increases
Solution Approach 1:
The patent segments the memory architecture into independent pseudo-split dies with separate interface circuitry, eliminating the need for CA data interleaving. Each pseudo-split die has its own command and address channels, allowing direct access without complex interleaving logic, thereby reducing device complexity while maintaining bandwidth utilization through parallel access paths.
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods are disclosed. An example memory module includes: a memory die a first pseudo-split die having first interface circuitry; and a second pseudo-split die having second interface circuitry; and a multiplexer external to the memory die, the multiplexer having a first port connected to the first interface circuitry, a second port connected to the second interface circuitry, and a third port connected to memory controller circuitry.