Pseudo-Synchronous TDM Multiplexer Logic for Asynchronous Clock Synchronization
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Solution Overview
Problem
Traditional Time Division Multiplexing (TDM) schemes face challenges in maintaining high transmission rates in heavily interconnected multi-device systems like ASIC prototypes due to difficulties in clock synchronization and oversampling delays, which limit system performance and resource efficiency.
Innovation Solution
The implementation of pseudo-synchronous TDM, where the number of data transmission slots is determined from the periods of the transmission and design clocks, allowing for slot synchronization without clock synchronization, using a slot counter to control input selection logic and generate synchronization signals, enabling efficient data transmission and reception across asynchronous clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous TDM is used to achieve high transmission performance, then transmission efficiency is improved, but clock synchronization complexity and cost increase
Solution Approach 1:
The patent extracts the synchronization function from the clock signal itself and implements it through separate synchronization packets transmitted within the TDM frame. This allows the clock signals to remain asynchronous while synchronization information is carried independently through dedicated packets, resolving the contradiction between high transmission efficiency and clock synchronization complexity
Solution Approach 2:
The patent introduces synchronization packets as an intermediary mechanism between transmitter and receiver. These packets carry timing and synchronization information that mediates the relationship between asynchronous clocks, enabling efficient TDM operation without requiring complex clock synchronization hardware
2Device complexity
If asynchronous TDM is used to simplify clock distribution, then synchronization complexity is reduced, but transmission slots become misaligned causing large delays
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-positioning synchronization packets at specific intervals within the TDM frame structure. This allows the receiver to anticipate and prepare for slot alignment points in advance, reducing the effective delay caused by asynchronous operation while maintaining simplified clock distribution
Solution Approach 2:
The patent implements periodic synchronization packets at regular intervals within the TDM frame structure. This periodic action allows the receiver to continuously realign with the correct time slots without requiring continuous complex synchronization, thereby reducing transmission delay while maintaining asynchronous operation
3Productivity
If high TDM ratio is used to share transmission channels, then resource efficiency is improved, but oversampling delay increases
Solution Approach 1:
The patent segments the high-ratio TDM transmission into multiple smaller sub-frames with embedded synchronization packets. This segmentation allows the receiver to process and realign with smaller intervals rather than waiting through the entire high-ratio cycle, reducing the effective oversampling delay while maintaining high resource efficiency through the overall high TDM ratio
Data Source
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AI summary
Methods and apparatuses to multiplex logic data pseudo synchronously are described. A representation of a multiplexer logic is generated to transmit data items asynchronously relative to a design clock. The data items may be transmitted under control of a transmission clock from a first integrated circuit to a second integrated circuit. A representation of a counter logic may be generated to couple with the multiplexer logic for transmitting the data asynchronously. Additionally, a representation of reset logic may be generated for a configuration to repeatedly reset the counter logic. Synchronization signals may be generated for a design clock cycle of a design clock driving the data items. The synchronization signals may be transmitted via the transmission clock asynchronous with the design clock. The data items may be transmitted via a number of transmission slots determined based on the clock cycles of the transmission clock and the design clock The total time for the transmission slots for transmitting the logic data may be less than the clock cycle of the design clock. One or more transmission slots within the clock cycle of the design clock may be used to transmit the synchronization data to indicate a new cycle to transmit the data items according to the design clock.