PTP Synchronization Architecture for Multi-SFP Transceiver Timing
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Solution Overview
Problem
Conventional synchronizing systems can only be electrically connected to four SFP transceivers, limiting their capacity to synchronize multiple devices.
Innovation Solution
A synchronizing system incorporating a phase-locked loop (PLL) unit, two network controllers, a processor, and a signal-adjusting device, allowing for the connection of more than four SFP transceivers through multiple clock-event and PTP signal generation and retiming processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single network controller is used in the conventional synchronizing system, then the system structure remains simple, but the system can only be electrically connected to four SFP transceivers at most
Solution Approach 1:
The patent divides the single network controller into two separate network controllers (first network controller and second network controller). Each network controller independently receives clock signals and synchronization signals from the PLL unit, generates clock events, and connects to multiple SFP transceivers. This segmentation allows the system to support more than four SFP transceivers while maintaining manageable complexity through modular design.
2Adaptability or versatility
If multiple network controllers are introduced to increase transceiver capacity, then the connection capacity increases, but the device complexity increases
Solution Approach 1:
Both network controllers are designed with identical functional capabilities: receiving clock signals and synchronization signals from the PLL unit, generating clock events based on these signals, and outputting PTP signals. This universal design allows each controller to independently serve multiple SFP transceivers, increasing overall system capacity while maintaining consistent operational patterns that simplify system management.
Solution Approach 2:
The patent combines the functions of multiple network controllers with the existing PLL unit and processor. The PLL unit serves both network controllers by providing clock signals and synchronization signals through multiple output interfaces, while the processor receives clock events from both controllers to generate coordinated PTP signals. This merging approach shares common resources to reduce overall system complexity.
3Adaptability or versatility
If the PLL unit outputs synchronization signal through multiple pin combinations, then more network controllers can be supported, but the signal distribution complexity increases
Solution Approach 1:
The synchronization signal output from the PLL unit is segmented into multiple independent signal paths through different pin combinations. Each pin combination (first pin and second pin for first network controller, third pin and fourth pin for second network controller) provides a dedicated signal pathway, allowing multiple network controllers to receive synchronized signals independently without signal interference or complex multiplexing.
Solution Approach 2:
The PLL unit acts as an intermediary that generates and distributes both clock signals and synchronization signals to multiple network controllers through dedicated pin combinations. This intermediary approach centralizes signal generation while providing organized, independent distribution paths to each controller, simplifying the overall signal distribution architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables synchronization of up to twelve SFP transceivers, enhancing the system's capacity to connect and synchronize external devices effectively.
Implementation Method 1
The PLL unit is configured to receive a local oscillator signal, to generate and output a clock signal having an operating frequency, to generate a synchronizing signal
Implementation Method 2
The signal-adjusting device is configured to receive the clock signal from the PLL unit and the first PTP signal from the first network controller, to operate according to the clock signal, to perform retiming on the first PTP signal
Data Source
AI summary
A synchronizing system includes a phase-locked loop (PLL), first and second network controllers (NCs), a retimer and a processor. The PLL receives a local oscillator (LO) signal, generates and outputs a clock signal and a synchronizing signal. The retimer and the first and second NCs operate according to the clock signal. The first/second NC generates a first/second clock-event signal based on the synchronizing signal. The processor generates a first/second Precision Time Protocol (PTP) signal based on the first/second clock-event signal, and transmits the first/second PTP signal to the first/second NC. The second NC delivers the second PTP signal to first transceivers. The retimer performs retiming on the first PTP signal, and delivers the same to second transceivers. In a master mode, the PLL unit generates the synchronizing signal based on the LO signal and a reference time signal received from a global navigation satellite system (GNSS).