PtSe2 Source-Drain Structure for Low-Tunneling FinFET Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with subthreshold slope and contact resistance in transistor devices.
Innovation Solution
The use of semimetallic source/drain structures formed from 2D material layers like PtSe2, where the conduction band and valence band are at different symmetry k-points, reduces unwanted tunneling and improves subthreshold slope and contact resistance by suppressing source-to-drain tunneling and enhancing thermal injection current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process difficulty increases and device reliability deteriorates
Solution Approach 1:
The patent changes the material parameter from conventional semiconductor materials to 2D material layers (such as transition metal dichalcogenides), which fundamentally alters the electrical and structural properties. This material parameter change enables the formation of reliable devices at smaller sizes by providing superior electrostatic control and reduced short-channel effects, thus resolving the contradiction between scaling down for productivity and maintaining reliability
Solution Approach 2:
The patent employs composite material structures combining 2D material layers with conventional semiconductor materials and dielectric layers. This composite approach integrates the benefits of 2D materials (atomically thin, high mobility, excellent electrostatic control) with the成熟 fabrication processes of conventional semiconductors, enabling reliable device formation at scaled dimensions while maintaining manufacturing feasibility
2Ease of manufacture
If conventional semiconductor materials are used at smaller sizes, then fabrication complexity increases, but subthreshold slope performance deteriorates and contact resistance increases
Solution Approach 1:
The patent changes the critical material parameter from bulk semiconductor to 2D material layers with atomic thickness, which fundamentally improves subthreshold slope by enabling better gate control and reducing leakage currents. The 2D material's unique electronic structure and surface properties directly address the subthreshold slope and contact resistance issues that plague conventional scaled devices
Solution Approach 2:
The 2D material layer acts as an intermediary between the gate electrode and the channel region, providing superior electrostatic coupling and control. This intermediary layer enables effective field effect modulation at scaled dimensions, improving subthreshold slope while maintaining compatibility with existing fabrication processes through standard deposition and patterning techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the subthreshold slope and reduces resistance in semiconductor devices, enhancing their performance and efficiency by utilizing semimetallic properties to minimize tunneling effects and optimize current transport mechanisms.
Implementation Method 1
the conduction band and valence band are at different symmetry k-points, reduces unwanted tunneling and improves subthreshold slope and contact resistance by suppressing source-to-drain tunneling
Implementation Method 2
improves subthreshold slope and contact resistance by suppressing source-to-drain tunneling and enhancing thermal injection current
Data Source
AI summary
A method includes forming a semiconductor fin protruding above a substrate; forming a first 2D material layer across the semiconductor fin; depositing a gate material layer over the first 2D material layer; etching the gate material layer and the first 2D material layer to form a gate structure and a patterned first 2D material layer under the gate structure; laterally growing a second 2D material layer from the patterned first 2D material layer to beyond the gate structure; after laterally growing the second 2D material layer, forming gate spacers respectively on opposite sidewalls of the gate structure; and after forming the gate spacers, forming a third 2D material layer on the second 2D material layer until a combination of the third 2D material layer and the second 2D material layer comprises at least three or more monolayers of PtSe2.