PUF OTP Memory Cell Layout Using Fuse Variability for IC Authentication

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Solution Overview

Problem

Existing one-time-programmable (OTP) memory devices face challenges in maintaining consistent functionality across different fabrication facilities due to manufacturing variability, necessitating independent optimization for each facility.

Innovation Solution

Implementing a physically unclonable function (PUF) memory device using efuse cells with two fuse resistors, where one resistor is randomly programmed to an open or short circuit, generating a unique PUF signature based on manufacturing variability, eliminating the need for secure digital memory and expensive hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If OTP memory devices are used to adjust circuitry after fabrication, then product functionality can be independently optimized for each manufacturing facility, but manufacturing variability causes inconsistency in device functionality across different fabrication facilities

Engineering Contradiction:
ImproveIndependent optimization capabilityVSAvoidFunctionality consistency
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The PUF memory device uses inherent manufacturing variability as a resource to automatically generate unique identifiers. Each device's physical characteristics during fabrication naturally create a distinct signature without requiring external programming or calibration, allowing the device to self-configure for facility-specific optimization while maintaining reliability through the uniqueness of its physical fingerprint

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The invention changes the approach from attempting to control manufacturing parameters to utilizing variations in manufacturing parameters. By measuring and leveraging the natural variability in physical characteristics (such as transistor threshold voltages or resistor values) that occur during fabrication, the system converts manufacturing inconsistency into a useful unique identifier that maintains both adaptability and reliability

Inventive Principle:
Principle #35Parameter changes

2Reliability

If secure digital memory is implemented to store unique identifiers, then device authenticity can be verified, but additional secure memory increases device complexity and cost

Engineering Contradiction:
ImproveDevice authenticity verificationVSAvoidAdditional secure memory
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts the unique identifier generation function from separate secure memory components and integrates it directly into the existing memory device structure. By using the memory device's own physical characteristics to generate the identifier, the system eliminates the need for additional secure memory hardware, reducing device complexity while maintaining authenticity verification capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The PUF memory device performs multiple functions using the same hardware structure: it stores data like a regular memory device while simultaneously generating unique identifiers through its physical characteristics. This multi-functionality eliminates the need for separate secure memory components, reducing overall device complexity while maintaining authenticity verification

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250357377A1PUF memory devices and methods of manufacturing thereof
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250357377A1 patent drawing
  • US20250357377A1 patent drawing
  • US20250357377A1 patent drawing

AI summary

A memory device includes an array comprising a plurality of one-time-programmable (OTP) memory cells; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate (CG) lines. Each of the OTP memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are coupled to a corresponding one of the BLs, while the first transistor and the second transistor are gated by a first one and a second one of the CG lines, respectively.