PUF Tie Cell Netlist Obfuscation for Secure IC Logic
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Solution Overview
Problem
Existing methods for protecting integrated circuit chips from hacking and reverse engineering are inadequate, as they fail to effectively prevent unauthorized access and counterfeiting, and do not sufficiently obscure the netlist of the chip.
Innovation Solution
The integration of tie cells with physically unclonable functions (PUFs) and XOR logic within the chip's digital logic, which generate constant logical values based on manufacturing-specific physical and electrical characteristics, making it difficult to determine the netlist and preventing unauthorized access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing protection methods are used for integrated circuit chips, then some basic security is provided, but the netlist can still be reverse engineered and unauthorized access is not effectively prevented
Solution Approach 1:
The chip is divided into multiple functional blocks, each containing tie cells with PUF circuits. The netlist is segmented into multiple sub-netlists corresponding to different functional blocks, making reverse engineering more difficult as each segment alone does not reveal the complete system architecture.
Solution Approach 2:
Tie cells are introduced as intermediary elements between functional blocks. These tie cells contain PUF circuits that generate unique identification values and constant logical values, acting as mediators that obfuscate the netlist connectivity information while maintaining functional integrity.
2Difficulty of detecting and measuring
If tie cells with PUF circuits are integrated into the chip, then netlist obfuscation is achieved and reverse engineering is prevented, but the device complexity increases
Solution Approach 1:
Tie cells are designed to perform multiple functions: they generate unique identification values through PUF circuits, produce constant logical values for logic tying, and provide netlist obfuscation. This multi-functionality reduces the need for separate circuits for each function, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The tie cells utilize physical parameters (electrical characteristics) that vary due to manufacturing process variations to generate unique PUF values. By changing the physical parameters rather than adding complex logical structures, the solution achieves netlist obfuscation with minimal increase in circuit complexity.
3Reliability
If PUF circuits are used to generate unique values, then chip identification and security are enhanced, but the manufacturing precision requirements increase due to reliance on process variations
Solution Approach 1:
The solution converts the potential harm of manufacturing process variations (which create inconsistencies) into a benefit by using these variations to generate unique PUF values for each chip. The manufacturing imprecisions that would normally be considered defects are instead exploited to create unclonable identification characteristics.
Solution Approach 2:
The PUF circuits automatically generate unique identification values based on their own physical characteristics resulting from the manufacturing process. Each chip's PUF circuit self-generates its unique identifier without requiring external programming or additional precision control, making the system self-service oriented.
Data Source
AI summary
A tie cell includes a first flip-flop having a physically unclonable function (PUF), a second flip-flop that generates a PUF key value, and logic that logically combines the PUF value and the PUF key value to generate an output signal having a constant logical value. The PUF value is based on a power-up value stored in the first flip-flop, which power-up value is generated based on physical and/or electrical characteristics produced from a manufacturing process. The output value is generated to tie digital logic to the constant logical value.