Clock Signal Pulse Feedback for Stable Smart Card Timing

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Solution Overview

Problem

Smart cards often generate unstable clock signals during data communication with hosts due to environmental factors like temperature and voltage fluctuations, which can disrupt data transfer efficiency.

Innovation Solution

A clock signal generator is implemented in semiconductor memory devices that counts pulses during a reference time, compares them to a reference value, and adjusts the clock signal accordingly to maintain stability, using a control unit and controller to ensure consistent signal generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If smart card generates its own clock signal during data communication with host, then the smart card can operate independently, but the clock signal becomes unstable due to environmental factors such as temperature and voltage

Engineering Contradiction:
Improveindependent operation capabilityVSAvoidclock signal stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the clock signal generator counts the number of pulses during a reference time period, compares this count with a reference value, and generates a control signal to adjust the clock signal generation. This closed-loop feedback system continuously monitors and corrects clock signal stability, resolving the contradiction by maintaining reliable clock signals while enabling independent operation.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the operational parameters of the clock signal generator by dynamically adjusting the number of pulses based on environmental conditions. The control signal modifies the clock signal generation parameters (pulse count during reference time) to compensate for temperature and voltage variations, thereby maintaining stability while preserving independent operation capability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the clock signal is adjusted frequently to maintain stability, then the clock signal remains stable under environmental changes, but the complexity of the control mechanism increases

Engineering Contradiction:
Improveclock signal stabilityVSAvoidcontrol mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The clock signal generator performs self-adjustment by automatically counting its own pulses, comparing the count with a reference value, and generating control signals to regulate its own operation. This self-service mechanism reduces the need for external control complexity while maintaining clock signal stability under environmental variations.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The simplified feedback loop directly compares the pulse count with a reference value and generates control signals accordingly. This straightforward feedback mechanism achieves effective clock signal stabilization without requiring complex control algorithms or additional components, thus resolving the contradiction between reliability and device complexity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8145935B2Clock signal generator for generating stable clock signal, semiconductor memory device including the same, and methods of operating
Publication Date: 2012.03.27 SAMSUNG ELECTRONICS CO LTD
  • US8145935B2 patent drawing
  • US8145935B2 patent drawing
  • US8145935B2 patent drawing

AI summary

A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.