Asynchronous Pulse Counter With Synchronous Readout for Audio Signals
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Solution Overview
Problem
Current circuits and devices for audio file processing, particularly for counting pulses from audio signals, are inefficient, lack low-frequency operation capabilities, and insufficient in power for effective signal processing.
Innovation Solution
A pulse counter circuit comprising an asynchronous counter synchronized by a clock signal, with a flip-flop for reading the counter value during specific synchronization phases, and integrated with a neural network for audio processing, operating at a frequency of 30-40 kHz, including acoustic characteristic extraction and digital signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If asynchronous counter is used for pulse counting, then counting power is improved, but circuit synchronization becomes difficult
Solution Approach 1:
The circuit is divided into two independent parts: an asynchronous counter section for high-power pulse counting and a synchronous readout section for reliable data retrieval. The asynchronous counter (U1) operates independently to count pulses with high power, while the synchronous readout circuit (U2, U3) is triggered by clock signal to read the count value, ensuring synchronization without compromising the counter's power.
Solution Approach 2:
A synchronous readout circuit acts as an intermediary between the asynchronous counter and the external system. This intermediary circuit is triggered by clock signal edges to transfer the counter value to output registers, ensuring that data readout is synchronized with the system clock while the counter itself continues to operate asynchronously with high power.
2Speed
If high-frequency operation is used, then processing speed is improved, but energy consumption increases
Solution Approach 1:
The readout operation is performed periodically rather than continuously. The synchronous readout circuit is triggered only at specific clock edges when data needs to be transferred, allowing the counter to operate continuously at high speed while the readout mechanism consumes energy only during necessary data transfers, reducing overall energy consumption.
3Measurement precision
If circuit complexity is increased to improve pulse counting capability, then counting accuracy is improved, but device complexity increases
Solution Approach 1:
The synchronization and readout functions are extracted as a separate synchronous circuit block, distinct from the asynchronous counter core. This allows the counter to maintain its simple, high-accuracy asynchronous structure while the readout circuit handles synchronization requirements, separating concerns and managing overall device complexity.
Data Source
AI summary
The present description relates to a pulse counter (200) comprising an asynchronous counter (201) and a circuit (205) configured to trigger a read operation of the value of said asynchronous counter, said circuit (205) being synchronized by a clock signal.