Pulse Output DDS Circuit With Edge Selection for Low-Jitter Clocks
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Solution Overview
Problem
Existing direct digital synthesis (DDS) circuits for generating multiple clock signals are inefficient in terms of power and speed, particularly in multi-port systems where multiple independent oscillating circuits are required, leading to high costs and operational challenges with higher reference clock frequencies and output clock frequencies.
Innovation Solution
A pulse output DDS circuit that uses a modulo-N counter and accumulator to generate a phase-indication signal, allowing dynamic control of the output clock frequency by selecting clock edges and incorporating a dynamic control interface to reduce spurious noise, enabling efficient generation of multiple non-related clock signals with reduced jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple independent oscillating circuits are used to generate multiple clock signals, then each port can receive and recover data at different rates, but the cost and device complexity increase significantly
Solution Approach 1:
A single reference oscillating circuit serves multiple ports simultaneously, replacing the need for multiple independent oscillating circuits. The phase-locked loops in each port are independently controlled to achieve different data rate adaptations while sharing the common reference clock source.
Solution Approach 2:
Multiple clock generation functions are merged into a single reference oscillating circuit. The patent combines the reference clock generation with multiple phase-locked loop controllers that can be independently adjusted to serve different data rate requirements across multiple ports.
2Speed
If the reference clock frequency is increased to improve speed, then clock generation accuracy improves, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the effective clock frequency for each port based on its specific data rate requirements. While the reference oscillating circuit operates at a high frequency to ensure accuracy, each phase-locked loop can operate at lower effective frequencies by using frequency division and phase adjustment, thereby reducing overall power consumption.
Solution Approach 2:
The patent changes the operating parameters of each phase-locked loop independently, allowing them to operate at optimal power consumption levels while maintaining accurate clock generation. The frequency control words and phase adjustors enable each port to use only the necessary frequency and phase precision for its specific data rate.
3Adaptability or versatility
If multiple phase-locked loops are used for frequency adjustment, then adaptability to different data rates improves, but device complexity and cost increase
Solution Approach 1:
Multiple phase-locked loops share a common reference oscillating circuit and control architecture. Each phase-locked loop is independently configurable through frequency control words and phase adjustors, providing adaptability to different data rates while reducing overall system complexity through component sharing.
Data Source
AI summary
A clock signal generator responsive to a frequency control word and a reference clock signal having a reference clock frequency fref. The clock signal generator generates an output clock signal having a frequency fgen, wherein fgen is less than fref. A modulo-N counter accepts the reference clock signal as input. The modulo-N counter generates a phase-indication signal of the reference clock. The phase indication signal has N clock phases repeating at a frequency of fref/N. An accumulator iteratively accumulates a frequency control word into a modulo-N adder and produces an accumulated value. One or more bits of the accumulated value is fed-back into the modulo-N adder for adding modulo N to the accumulated value in the next iteration. N of the modulo-N adder is the same integer as in the modulo-N counter. A clock edge selector receives as inputs the phase indication signal and one or more bits of the accumulated value and by comparing the inputs selects an edge of the reference clock signal upon which to toggle the state of the output clock signal. The clock edge selector preferably selects the edge from: (i) only rising edges of the reference clock signal, (ii) only falling edges of the reference clock signal or (iii) both rising and falling edges of the reference clock signal. The clock edge selector selects between a rising edge and a falling edge of the reference clock signal preferably based on one or more bits of the accumulated value.