Pulse Latch Clock Regeneration for Minimal Setup and Launch Delay
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Solution Overview
Problem
In modern data processing systems, particularly those operating at multi-gigahertz speeds, the setup and launch delays through latches contribute significantly to cycle time, and existing latch designs face challenges with pulse signal degradation and sensitivity to process variations, necessitating improved latch triggering circuits and pulse shaping solutions that are scalable across various processes.
Innovation Solution
The implementation of clock regeneration circuitry that generates two clock signals with similar propagation characteristics, allowing for the creation of either an implicit or explicit data propagation window, which minimizes setup and launch delays by using clock signals with identical or time-shifted RC characteristics to optimize data transfer through latches in a datapath.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single pulse generator is used to generate pulses for an entire datapath, then the initial pulse shape is proper, but the pulse degrades as it propagates across latches due to RC network attenuation
Solution Approach 1:
The patent divides the single pulse generation function into multiple distributed pulse generation units, with each latch having its own pulse generation circuit. This segmentation prevents pulse degradation by generating fresh pulses locally at each latch rather than transmitting a single pulse across the entire datapath.
Solution Approach 2:
The patent introduces delay elements as intermediary components between the clock signal source and each latch's pulse generation circuit. These delay elements are designed with matched RC characteristics to compensate for transmission delays and ensure synchronized pulse generation across all latches despite varying path lengths.
2Speed
If pulse latch topology is used to minimize setup and launch delay, then speed is improved, but the pulse generation circuit becomes very sensitive to process variation
Solution Approach 1:
The patent employs delay elements with carefully engineered RC time constants that are designed to be relatively insensitive to process variations. By optimizing the R and C values to achieve matched delay characteristics across different process conditions, the system maintains reliable pulse generation while preserving the fast speed benefits of pulse latch topology.
3Ease of operation
If multiple clocks are used in master-slave latches to enable master and slave portions, then data propagation is enabled, but setup and launch delay become significant in multi-gigahertz processors
Solution Approach 1:
The patent uses periodic clock signals to generate narrow pulses that briefly enable data propagation through each latch. This periodic pulsing action allows data to be captured and propagated with minimal setup and launch delay, as the pulse width is optimized to be just sufficient for data transfer without requiring the extended timing windows of traditional master-slave latches.
Data Source
AI summary
The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The first clock signal is a version of the system clock and the second control signal is a time-shifted, inverted version of the system clock signal. Each of the individual latches in a datapath comprises data propagation logic. In one embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an “implicit” pulse. In another embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an “explicit” pulse. The implicit and explicit pulses are used to control the transmission gate of the latch to provide propagation of data through the latch with minimal latency.