Pulse-Enabled Register Circuit for Time Borrowing and Timing Error Detection
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Solution Overview
Problem
Integrated circuits face processing errors due to delays in clock signals, particularly in low supply voltage environments, where conventional flip-flops do not allow time borrowing, leading to potential metastability and energy inefficiency.
Innovation Solution
A register circuit design using pulse-enabled subregister stages with a delayed triggering signal to allow time borrowing, applicable to both single and double edge triggered flip-flops, enabling the detection of timing errors and announcement to other circuit parts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional flip-flops are used to store digital values in pipelines, then the circuit structure is simple and reliable, but time borrowing is not allowed causing processing delays and energy inefficiency
Solution Approach 1:
The flip-flop is divided into two pulse-enabled subregister stages (first and second subregisters) that can be independently controlled. This segmentation allows the first subregister to capture data earlier than the second subregister, enabling time borrowing while maintaining the overall flip-flop structure.
Solution Approach 2:
The circuit uses dynamic clocking with pulse-enabled subregisters where the enabling pulse width and timing can be adjusted. This dynamic control allows the circuit to adaptively borrow time when needed while maintaining normal operation, resolving the contradiction between processing speed and energy consumption.
2Reliability
If the supply voltage is increased to prevent time errors, then timing reliability is improved, but energy consumption increases
Solution Approach 1:
The first pulse-enabled subregister captures the data value earlier in the clock cycle than the second subregister. By performing this preliminary capture action, the circuit ensures that data is ready before the next clock edge, preventing time errors without requiring increased supply voltage.
3Adaptability or versatility
If latches are used instead of flip-flops to allow time borrowing, then processing flexibility is improved, but metastability issues and error propagation occur
Solution Approach 1:
The second pulse-enabled subregister acts as an intermediary between the first subregister and the output. It captures the value from the first subregister and holds it until the appropriate clock edge, mediating the time borrowing process and preventing metastability from propagating to subsequent circuit elements.
Solution Approach 2:
The circuit includes timing event observation logic that monitors for timing violations and generates error signals. This feedback mechanism detects when time borrowing occurs and can trigger corrective actions, ensuring reliability while maintaining adaptability.
4Measurement precision
If Razor error correction is implemented, then time error detection is improved, but an obligatory delay of one clock cycle is introduced
Solution Approach 1:
The first pulse-enabled subregister performs preliminary data capture earlier in the clock cycle, so that when timing errors occur, the correction can be applied within the same clock cycle rather than requiring a full clock cycle delay as in traditional Razor circuits.
Data Source
AI summary
Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well as a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become available for said subsequent circuit element. A sequence of first and second pulse-enabled subregister stages is used to temporarily store said digital value. Said triggering signal is provided to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage. The length of the delay is a fraction of a cycle of the triggering signal. A timing event observation signal is output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal.