Pulse Widening Address Decoding for Long-Distance Memory Signals
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Solution Overview
Problem
Existing memory systems suffer from command execution errors due to increased skew and reduced pulse width of address signals after long-distance transmission, leading to inaccurate command sampling and execution failures.
Innovation Solution
Implement a pulse widening circuit to increase the pulse width of address signals, coupled with an address decoding circuit to ensure accurate command execution by providing more timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address signal is transmitted over long distance, then memory can access more banks, but pulse width decreases and skew increases leading to command execution errors
Solution Approach 1:
The pulse widening circuit performs preliminary action by extending the pulse width of the address signal before it undergoes degradation during long-distance transmission. This proactive measure ensures that even after transmission losses, the signal maintains sufficient pulse width for reliable command sampling and execution.
2Measurement precision
If address signal pulse width is increased to improve sampling accuracy, then command execution success rate improves, but signal transmission time increases
Solution Approach 1:
The pulse widening is applied selectively and locally to only the address signal that requires long-distance transmission, rather than uniformly increasing pulse widths of all signals. This targeted approach improves sampling accuracy for critical paths without unnecessarily extending transmission time for other signals.
Data Source
AI summary
The present disclosure provides a signal processing circuit and a memory. The signal processing circuit includes a pulse widening circuit and an address decoding circuit. The pulse widening circuit is configured to widen a pulse width of an address signal through a command signal, thereby generating a widened address signal. An input terminal of the address decoding circuit is coupled to an output terminal of the pulse widening circuit for decoding the widened address signal to generate a decoded address signal.