Pulse-Width Delay Circuit for Stable High-Frequency Timing
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Solution Overview
Problem
Conventional delay circuits experience unstable operation when input signals are activated at high frequencies due to the inability to effectively manage varying delay values.
Innovation Solution
A delay circuit design incorporating a pulse generation unit and output unit, which includes synchronization, shift, selection, and SR latch sections to generate a pulse signal with a width corresponding to delay information, ensuring stable operation by selectively activating output signals based on delay information and clock synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple shift units are coupled in series to achieve variable delay values, then the delay circuit can provide multiple delay options, but the operation becomes unstable at high input signal frequencies
Solution Approach 1:
The delay circuit is divided into multiple independent shift units (101-104), each capable of delaying the input signal by 1 clock cycle. These units are coupled in series to provide variable delay values by selecting different combinations of units. This segmentation allows the circuit to achieve adaptability while maintaining stability through controlled activation of individual units based on delay information signals.
2Productivity
If the delay circuit operates with high frequency input signals, then the productivity increases, but the operation stability deteriorates
Solution Approach 1:
The delay information signal is prepared in advance to control which shift units should be activated. The selection unit 120 uses this pre-prepared delay information to determine the appropriate combination of shift units to activate before the high-frequency input signal arrives. This preliminary action ensures that even at high frequencies, the circuit has time to configure the correct delay path, maintaining operation stability while achieving high productivity.
Data Source
AI summary
A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.