Pulse-Width Equalizer for Inter-Symbol Interference Removal
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Solution Overview
Problem
Existing semiconductor memory devices experience inter symbol interference (ISI) due to signal distortion between the device and a memory controller, leading to decreased data transmission speed and reliability, especially in high-speed interfaces where feedback within a unit interval is not feasible.
Innovation Solution
An equalizer is implemented with first and second pulse width controllers to increase the pulse widths of logic levels, samplers to generate sampled signals, and multiplexers to output these signals based on previous data bits, effectively removing ISI without requiring feedback within a unit interval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signal transmission is performed at high speed between semiconductor memory device and memory controller, then data transmission speed is improved, but signal distortion occurs causing inter symbol interference
Solution Approach 1:
The equalizer performs preliminary equalization processing on the data signal before sampling, compensating for signal distortion and inter symbol interference in advance. This preliminary action ensures that the data can be accurately received even at high transmission speeds by pre-correcting the signal degradation that occurs during transmission.
Solution Approach 2:
The equalizer acts as an intermediary component between the semiconductor memory device and memory controller, processing the data signal to remove inter symbol interference. This intermediary processing enables reliable high-speed data transmission by mediating the signal quality between the two devices.
2Measurement precision
If pulse width of data signal is increased to improve identification margin, then data reception accuracy is improved, but data transmission speed decreases
Solution Approach 1:
The equalizer dynamically adjusts the pulse width of the data signal as a variable parameter to optimize both identification accuracy and transmission speed. By changing the pulse width parameter based on signal conditions, the system achieves adequate identification margins without permanently reducing transmission speed, as the pulse width adjustment is part of the equalization process rather than a fixed limitation.
3Reliability
If equalization processing is performed to remove inter symbol interference, then data reliability is improved, but device complexity increases
Solution Approach 1:
The equalizer is divided into multiple functional units including pulse width controllers, samplers, and multiplexers that process different aspects of the signal independently. This segmentation allows each unit to perform a specific function, making the overall complex equalization process manageable and implementable through modular components.
Solution Approach 2:
The equalizer employs dynamic control mechanisms where pulse width controllers and multiplexers adaptively adjust signal parameters based on real-time conditions. This dynamic operation enables the equalizer to handle varying signal conditions effectively, improving reliability while managing complexity through adaptive rather than purely static designs.
Data Source
AI summary
An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.