Pulsed Bias Generation for Fast MRAM Sense Amplifier Wake-Up

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Solution Overview

Problem

Conventional magneto-resistive memory bias generators face challenges with high activation times and large settling times due to analog bias signals, which negatively impact access time and static power consumption, particularly during idle or wake-up periods.

Innovation Solution

A pulsed activation scheme for bias generators is implemented, utilizing multiple parallel distributed bias generators with instantaneous turn-on capabilities and high slew rate amplifiers to achieve fast activation and low static power consumption, along with configurable bias generators to maintain a stable bias signal during low activity periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If conventional analog bias generators are used to regulate read current, then bias signal stability is improved, but activation time increases and memory performance degrades

Engineering Contradiction:
Improvebias signal stabilityVSAvoidactivation time
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The bias generator is divided into multiple parallel distributed bias generators, each capable of independent operation. This segmentation allows the system to achieve fast activation by distributing the activation load while maintaining stable bias signals through coordinated operation of multiple units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a pulsed activation scheme where bias generators are activated in controlled pulses rather than continuously. This periodic action enables fast wake-up by activating only when needed, reducing overall activation time while maintaining bias stability during active periods.

Inventive Principle:
Principle #19Periodic action

2Adaptability or versatility

If conventional bias generators with heavy capacitive loading are used for active tuning, then read reference resistance tuning capability is improved, but settling time during wake-up increases

Engineering Contradiction:
Improveread reference resistance tuning capabilityVSAvoidsettling time during wake-up
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

Multiple parallel distributed bias generators are used to share the capacitive loading burden. Each generator handles a portion of the total capacitance, enabling faster settling during wake-up while maintaining the ability to actively tune read reference resistance through coordinated control of the distributed units.

Inventive Principle:
Principle #1Segmentation

3Speed

If bias generators are activated continuously to ensure fast response, then activation time is reduced, but static power consumption increases

Engineering Contradiction:
Improveactivation speedVSAvoidstatic power consumption
Core Design Contradiction:
SpeedVSUse of energy by stationary object

Solution Approach 1:

The patent implements pulsed activation where bias generators are activated only during needed operations (read operations) rather than continuously. This periodic activation maintains fast response capability when activated while dramatically reducing static power consumption during idle periods when activation is not required.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The bias generator system transitions from a static continuous operation mode to a dynamic pulsed operation mode. The system adapts its activation state based on operational requirements, being active during read operations for fast response and inactive during idle periods for low power consumption.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11164616B2Bias generation circuitry
Publication Date: 2021.11.02 ARM LTD
  • US11164616B2 patent drawing
  • US11164616B2 patent drawing
  • US11164616B2 patent drawing

AI summary

Various implementations described herein are directed to device having a memory block and a sense amplifier coupled to the memory block. The device may include a bias generator that applies a bias signal to the sense amplifier for regulating read current to the sense amplifier for faster activation of the memory block.