Pulsed Sputtering TaN Barrier for High Aspect Ratio Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor chips with high aspect ratio vias face challenges in achieving uniform metallization due to the formation of high resistivity beta-tantalum phase during deposition, which can lead to performance issues and substrate damage, especially when using copper for interconnects.
Innovation Solution
A method involving high current, low duty cycle pulsed sputtering to deposit a TaN seed layer followed by a tantalum layer, using a DC power supply with pulsed DC voltage and a high-frequency signal to promote the growth of low resistivity alpha-tantalum phase, reducing the formation of beta-tantalum and enhancing coverage on high aspect ratio features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional sputtering methods are used to deposit metallization layers, then the deposition process is simple and fast, but the formed tantalum layer has high resistivity due to beta-phase formation and non-uniform coverage on high aspect ratio vias
Solution Approach 1:
The patent applies pulsed DC voltage instead of continuous voltage, using periodic on/off cycles to control the sputtering process. This periodic action allows precise control of deposition parameters, enabling uniform coverage on high aspect ratio vias while preventing beta-phase formation through controlled pulse timing and duty cycle.
Solution Approach 2:
The patent changes multiple deposition parameters including voltage amplitude, pulse frequency, duty cycle, and gas composition (introducing nitrogen to form TaN). These parameter changes transform the deposition process to produce alpha-phase tantalum with low resistivity and uniform coverage, resolving the contradiction between coverage quality and process simplicity.
2Reliability
If copper is used for metallization to improve heat dissipation and reduce resistivity, then electrical performance improves, but copper diffuses into silicon substrate causing damage
Solution Approach 1:
The patent introduces a TaN/tantalum barrier layer structure as an intermediary between copper interconnects and silicon substrate. This barrier layer prevents copper diffusion into silicon while maintaining low electrical resistivity, thus preserving electrical performance without causing substrate damage.
Solution Approach 2:
The patent uses a composite barrier structure combining TaN and alpha-tantalum layers. This composite material provides both diffusion barrier functionality and low electrical resistivity, enabling safe use of copper interconnects while protecting the silicon substrate.
3Manufacturing precision
If high current and low duty cycle pulsed sputtering is used to deposit TaN and tantalum layers, then low resistivity alpha-phase is achieved with uniform coverage, but the process requires precise control of multiple parameters
Solution Approach 1:
The pulsed DC voltage application with specific duty cycles (e.g., 10% or 20%) creates periodic plasma conditions that favor alpha-phase formation. The periodic on/off cycling allows precise control of ion bombardment energy and deposition rate, achieving uniform coverage while managing process complexity through standardized pulse parameters.
Solution Approach 2:
The patent optimizes multiple parameters including pulse frequency (e.g., 100-1000 Hz), duty cycle (10-20%), voltage amplitude, and nitrogen partial pressure to achieve the desired alpha-phase structure. These coordinated parameter changes produce consistent results despite the increased control requirements.
4Productivity
If via aspect ratio increases to enable higher density interconnects, then device density improves, but uniform side wall coverage becomes difficult to achieve
Solution Approach 1:
The pulsed DC sputtering creates periodic plasma conditions that enhance ion bombardment during the on-phase, promoting conformal deposition on vertical sidewalls. The off-phase allows adatom migration and stress relaxation, enabling uniform coverage even on high aspect ratio structures with improved device density.
Solution Approach 2:
The patent adjusts deposition parameters including increasing nitrogen content to form TaN, optimizing pulse duration and frequency, and controlling substrate bias to enhance vertical direction deposition. These parameter changes enable uniform side wall coverage on high aspect ratio vias, supporting higher device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reliable deposition of a low resistivity tantalum layer with improved uniformity and reduced substrate damage, suitable for copper interconnects, facilitating faster and cost-effective fabrication of metallization structures with enhanced performance.
Implementation Method 1
A method of depositing a TaN/Ta barrier layer structure suitable for use with copper interconnects and which is deposited by physical vapour deposition, in particular, sputtering
Implementation Method 2
applying a power supply between an anode and a cathode in a plurality of pulses, the cathode including the target
Implementation Method 3
The pulsed power supply is applied with a high current and low duty cycle and, in particular, the pulses have a frequency in the range 10 Hz to 1000 Hz
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
A method of depositing a metallization structure (1) comprises depositing a TaN layer (4) by applying a power supply between an anode and a target in a plurality of pulses to reactively sputter Ta from the target onto the substrate (2) to form a TaN seed layer (4). A Ta layer (5) is deposited onto the TaN seed layer (4) by applying the power supply in a plurality of pulses and applying a high-frequency signal to a pedestal supporting the substrate (2) to generate a self-bias field adjacent to the substrate (2).