Punch-Through Stopper Layer for High Breakdown-Voltage Transistors
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Solution Overview
Problem
In semiconductor devices with high breakdown-voltage transistors, the formation of an impurity diffusion region directly below the STI leads to deteriorated device characteristics, especially as devices shrink, and increases process costs due to the need for fine photolithography and potential impurity scattering into active regions.
Innovation Solution
A p-type punch-through stopper layer is formed below the source and drain layers of high breakdown-voltage transistors to prevent depletion layer extension and leakage current, eliminating the need for an impurity diffusion region and maintaining transistor characteristics even at smaller sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an impurity diffusion region is formed directly below the STI to prevent punch-through, then leakage current between transistors is reduced, but device characteristics deteriorate with shrinking semiconductor devices
Solution Approach 1:
A punch-through prevention layer is introduced as an intermediary structure between the STI and the substrate. This layer specifically addresses the punch-through issue without requiring impurity diffusion regions that would deteriorate device characteristics, thus resolving the contradiction between reliability improvement and manufacturing precision maintenance
Solution Approach 2:
The isolation structure is segmented into multiple functional components: the STI for basic isolation and the punch-through prevention layer for specific punch-through prevention. This segmentation allows each component to perform its dedicated function without interfering with device characteristics, solving the contradiction between preventing leakage current and maintaining manufacturing precision
2Reliability
If an impurity diffusion region is formed directly below the STI, then electrical isolation between transistors is improved, but process costs increase due to fine photolithography requirements
Solution Approach 1:
The punch-through prevention layer serves as an intermediary structure that provides electrical isolation without requiring the fine photolithography processes needed for impurity diffusion regions. This reduces manufacturing complexity and cost while maintaining reliable electrical isolation between transistors
Solution Approach 2:
The punch-through prevention layer can be implemented using simpler, more cost-effective materials and processes compared to precision impurity diffusion regions. This approach achieves the necessary electrical isolation at lower process costs by using a dedicated isolation layer rather than relying on precisely controlled impurity diffusion
3Area of moving object
If the STI width is reduced to improve integration, then device size is reduced, but punch-through occurs between adjacent transistors
Solution Approach 1:
The isolation function is segmented between the STI (providing basic physical separation) and the punch-through prevention layer (providing electrical isolation). This segmentation allows the STI width to be reduced for better integration while the punch-through prevention layer maintains reliable electrical isolation between adjacent transistors
Solution Approach 2:
The solution moves from relying solely on horizontal STI width for isolation to adding a vertical dimension with the punch-through prevention layer. This layer, positioned between the STI and substrate, provides the necessary electrical isolation even when the horizontal STI width is minimized, enabling better device integration without sacrificing reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents punch-through and leakage currents between transistors, allowing for reliable electrical isolation without deteriorating transistor characteristics, enabling narrower STI widths and improved integration of high breakdown-voltage transistors without the need for impurity diffusion regions.
Implementation Method 1
depletion layers of two adjacent high breakdown-voltage transistors to come into contact with each other
Implementation Method 2
a technology of forming an impurity diffusion region directly below a STI
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, an element isolation insulating film dividing an upper portion of the substrate into a plurality of first active regions, a source layer and a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The source layer and the drain layer are formed in spaced to each other in an upper portion of each of the first active regions. The first punch-through stopper layer is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region. The second punch-through stopper layer and the drain layer are separated in the channel region.