Punchthrough Protection Layer in DRAM Transistor Trenches
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Solution Overview
Problem
Semiconductor transistors face challenges with punchthrough issues between source and drain regions due to reduced design rules, leading to increased leakage current and unstable interfacial states, particularly in trench gate structures with different oxide layers.
Innovation Solution
Incorporating a punchthrough protection layer within channel-portion holes of transistors, where a channel-portion layer and word line patterns are stacked, and using an epitaxial layer as the channel region to prevent punchthrough, thereby stabilizing the interface and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel region length is increased to prevent punchthrough, then the integration degree increases, but the distance between source and drain regions decreases causing punchthrough
Solution Approach 1:
The patent introduces a vertical dimension solution by forming a punchthrough protection layer at the bottom of the channel-portion hole, extending downward from the main surface of the semiconductor substrate. This vertical structure prevents punchthrough between source and drain regions without requiring an increase in horizontal channel length, thus maintaining high integration density while improving reliability.
Solution Approach 2:
The punchthrough protection layer acts as an intermediary structure between the source and drain regions. This intermediate layer physically blocks the direct path for punchthrough current while allowing the channel region to maintain its compact horizontal dimensions for high integration.
2Ease of manufacture
If an etching process is performed to form a trench gate structure, then the transistor structure is formed, but an unstable interfacial state is created causing leakage current
Solution Approach 1:
The patent applies preliminary action by forming the punchthrough protection layer at the bottom of the channel-portion hole before forming the gate structure. This pre-formed protective layer stabilizes the interface state before subsequent processing steps, preventing the creation of unstable interfaces that would lead to leakage current.
Solution Approach 2:
The patent changes the physical and chemical parameters of the interface by introducing the punchthrough protection layer, which modifies the interface state from unstable to stable. This parameter change prevents the formation of leakage paths while maintaining the manufacturability of the trench gate structure.
3Ease of manufacture
If different oxide layers are used on the bottom and sidewall of the trench, then the gate oxide layer is formed, but leakage current increases and breakdown voltage decreases
Solution Approach 1:
The patent applies local quality by positioning the punchthrough protection layer specifically at the bottom of the channel-portion hole where punchthrough occurs, rather than using different oxide layers on bottom and sidewall. This localized protection maintains uniform gate oxide properties while preventing punchthrough and maintaining breakdown voltage.
Data Source
AI summary
According to some embodiments of the invention, transistors of a semiconductor device have a punchthrough protection layer, and methods of forming the same are provided. A channel-portion hole extends downward from a main surface of a semiconductor substrate. A punchthrough protection layer and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line pattern fills an upper portion of the channel-portion hole, and is formed on the semiconductor substrate. The word line pattern is formed to have a word line and a word line capping layer pattern stacked thereon, and the channel-portion layer is a channel region. The punchthrough protection layer can reduce a leakage current of a capacitor of the transistor embodied in a DRAM.