Printed Wiring Board Warping Control via Insulation Thickness
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Solution Overview
Problem
Printed wiring boards face issues with warping and surface undulations due to thermal expansion differences between semiconductor elements and insulation layers, leading to reduced mounting yield and connection reliability, especially when large-sized semiconductor elements with fine-pitched terminals are mounted on one side.
Innovation Solution
A printed wiring board design featuring a first conductive layer embedded within a resin insulation interlayer, with a thicker adjacent resin insulation interlayer to balance thermal expansion and reduce warping, and a second conductive layer formed on the opposite side, along with alternating layers of resin insulation and conductive layers to create a flat surface for mounting, enhancing connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional buildup wiring board structure is used with uniform thickness insulation layers, then manufacturing is simpler, but warping and surface undulations occur due to thermal expansion differences
Solution Approach 1:
The patent applies local quality by varying the thickness of resin insulation interlayers at different locations. Specifically, the second resin insulation interlayer adjacent to the first conductive layer is made thicker than other insulation layers, creating a localized thickness variation that compensates for thermal expansion differences and reduces warping without requiring complete structural redesign.
Solution Approach 2:
The patent changes the physical parameter of insulation layer thickness to resolve the contradiction. By adjusting the thickness parameter of the second resin insulation interlayer to be greater than other insulation layers, the board achieves better dimensional stability and reduced warping while maintaining manufacturing feasibility.
2Adaptability or versatility
If large-sized semiconductor elements are mounted on one side, then functionality is improved, but warping increases due to thermal expansion differences
Solution Approach 1:
The patent directly addresses thermal expansion effects by designing the second resin insulation interlayer with greater thickness adjacent to the first conductive layer. This thicker insulation layer compensates for the thermal expansion forces generated by large-sized semiconductor elements, maintaining board flatness and stability while preserving mounting capability.
3Manufacturing precision
If first conductive layer is embedded in resin insulation interlayer, then surface flatness is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the conductive layer configuration into two distinct types: the first conductive layer is embedded in the resin insulation interlayer to achieve flatness, while the second conductive layer is formed on the surface for electrical connections. This segmented approach allows each layer to serve its specific function optimally.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces warping and surface undulations, improving the mounting yield and connection reliability of electronic components by balancing thermal expansion and maintaining a flat surface for mounting, thereby enhancing the overall performance of the printed wiring board.
Implementation Method 1
warping and surface undulations due to thermal expansion differences between semiconductor elements and insulation layers
Data Source
AI summary
A printed wiring board includes a first interlayer, a first conductive layer on first-surface side of the first interlayer, a second conductive layer on second-surface side of the first interlayer, a first buildup layer including interlayers and conductive layers and formed on first surface of the first interlayer, and a second buildup layer including interlayers and conductive layers and formed on second surface of the first interlayer. The first conductive layer is formed such that the first conductive layer is embedded in the first interlayer and exposing surface on the first surface of the first interlayer, the second conductive layer is formed on the second surface of the first interlayer, and the interlayers in the first buildup layer include a second interlayer positioned adjacent to the first conductive layer and having the greatest thickness among the first interlayer and interlayers in the first and second buildup layers.