Post Write Erase Conditioning for Charge Trapping Memory
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Solution Overview
Problem
Non-volatile memory systems, such as flash memory, face data retention issues due to charge loss and increased vulnerability as cell dimensions shrink, leading to elevated defect levels and compromised data integrity, especially at high temperatures.
Innovation Solution
Implementing post write erase conditioning (PWEC) to reprogram deeply erased cells by identifying and modifying the erase state with higher voltage, thereby tightening the erase distribution and reducing lateral charge movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell dimensions are scaled down to increase capacity per unit area, then storage density is improved, but data retention and reliability deteriorate due to increased charge loss and lateral charge movement
Solution Approach 1:
The patent applies parameter changes by modifying the voltage distribution within memory cells through selective cell conditioning. Specifically, it adjusts the verify voltage thresholds and applies targeted programming pulses to cells in the erased state that exhibit low voltage characteristics, thereby tightening the erase distribution and reducing lateral charge movement without changing the physical cell dimensions.
2Quantity of substance
If memory cell dimensions are scaled down, then capacity per unit area is improved, but manufacturing precision and defect levels worsen
Solution Approach 1:
The patent implements self-service through iterative cell conditioning that automatically identifies and corrects defective or improperly erased cells. The system performs read operations to identify cells with voltage below the threshold, then reprograms them through additional programming pulses, and verifies the correction. This self-correcting mechanism compensates for manufacturing defects without requiring higher manufacturing precision.
3Reliability
If higher voltage is applied to reprogram deeply erased cells, then data retention is improved by tightening erase distribution, but energy consumption increases
Solution Approach 1:
The patent applies partial action by selectively conditioning only those cells that require it - specifically, cells in the erased state with voltage below the verify threshold. Rather than reprogramming all cells in a block, the system identifies and treats only the subset of cells with improper erase voltage, thereby reducing overall energy consumption while still achieving the goal of tightening the erase distribution for improved data retention.
4Reliability
If post write erase conditioning is performed on all cells, then data retention is improved, but processing time and productivity are reduced
Solution Approach 1:
The patent applies segmentation by dividing the memory block into individual cell units and processing them selectively based on their specific voltage characteristics. Instead of applying uniform conditioning to all cells, the system segments the processing to target only those cells identified as deeply erased through read operations and threshold comparisons, thereby reducing overall processing time while maintaining data retention improvements.
Data Source
AI summary
A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.