Phase-Shifted Clock PWM Circuit for Precise Pulse Width Control
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Solution Overview
Problem
Existing PWM signal control systems lack high-resolution control over the timing of rising and falling edges, particularly in applications requiring precise pulse width modulation, which limits their ability to produce desired output voltages efficiently.
Innovation Solution
A circuit that generates a set of phase-shifted clocks from a base PWM pulse, allowing a CPU core to specify the timing of edges and adjust pulse width by using a selection circuit and flip-flops clocked with these clocks, enabling precise control over PWM pulse width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional PWM control systems are used, then the system structure is simple, but the control resolution over rising and falling edges is insufficient
Solution Approach 1:
The patent segments the PWM pulse generation into multiple discrete time slots by dividing the pulse period into N equal intervals and generating N phase-shifted clocks. Each clock corresponds to a specific time slot, allowing independent control of rising and falling edges at different resolution levels. This segmentation enables high-resolution edge timing control without requiring complex continuous adjustment mechanisms.
Solution Approach 2:
The patent introduces a temporal dimension by generating multiple phase-shifted clock signals with different phase offsets. Instead of controlling pulse width through a single continuous parameter, the system uses discrete time slots across multiple phases, transforming the control from a one-dimensional continuous adjustment to a multi-dimensional discrete selection process, thereby achieving higher resolution.
2Measurement precision
If delay lines are added to achieve precise pulse width control, then the control precision improves, but the power consumption increases
Solution Approach 1:
The patent replaces traditional analog delay line mechanisms with a digital clock selection approach. Instead of using continuous variable delay circuits that consume power across their entire range, the system uses discrete phase-shifted clocks that are selectively enabled. This substitution of mechanical/analog delay mechanisms with digital clock gating reduces power consumption while maintaining precision.
3Reliability
If traditional PWM generation methods are used, then the circuit is simple, but runtime calibration is required to maintain accuracy
Solution Approach 1:
The patent performs preliminary action by pre-generating N phase-shifted clock signals with fixed phase offsets during system initialization or design phase. These clocks are divided into M groups where each group corresponds to a specific time slot. This preliminary structuring eliminates the need for runtime calibration because the phase relationships are established beforehand and remain stable, improving reliability without adding calibration complexity.
Data Source
AI summary
A circuit includes a base pulse generator to generate a first pulse width modulated (PWM) pulse, a first clock generation circuit to generate M clocks of a first frequency and phase-shifted with respect to each other, and a second clock generation circuit to receive the M clocks and to generate N clocks each at a second lower frequency and the M clocks are phase-shifted with respect to each other. Each of a plurality of flip-flops includes a clock input to receive a different one of the N clocks, a data input coupled to receive the first PWM pulse, and a flip-flop output. A selection circuit includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit provides, responsive to a control signal, a selected one of the flip-flop outputs as the selection circuit output.