PWM Analog Signal Circuit With Ripple Sampling and Smaller LPF Area
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Solution Overview
Problem
Existing digital interfaces face challenges in efficiently passing voltage level information through pulse width modulation (PWM) signals due to voltage ripple issues, which require large device areas for low pass filters (LPFs) and are not effectively addressed by cascading multiple LPFs.
Innovation Solution
A circuit comprising a buffer, a 2nd or higher order low pass filter (LPF), and a switched capacitor circuit is used to generate a PWM-controlled analog signal, with sampling at the rising and/or falling edge of the PWM signal to remove voltage ripple, thereby reducing device area and achieving a 90×(2n+1) degree phase shift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a low pass filter with very low cut off frequency is used, then voltage ripple is reduced, but device area increases
Solution Approach 1:
The patent changes the operating parameters of the low pass filter by using a higher cut off frequency (e.g., 1/8 to 1/4 of PWM frequency instead of traditionally lower frequencies). This parameter change allows achieving acceptable voltage ripple reduction with significantly smaller RC component values, thereby reducing the filter's physical area on the chip while still meeting performance requirements.
Solution Approach 2:
The patent introduces periodic sampling action at specific phases of the PWM signal cycle. By sampling the filter output at strategically chosen times (e.g., at the center of PWM pulses or at specific phase angles), the system effectively reduces voltage ripple through temporal averaging without requiring excessive filtering in the time domain, thus avoiding large device area.
2Object-generated harmful factors
If multiple low pass filters are cascaded to improve attenuation, then voltage ripple is reduced, but device complexity increases
Solution Approach 1:
Instead of cascading multiple filters, the patent achieves equivalent or better attenuation by optimizing the parameters of a single filter stage - specifically by carefully selecting the cut off frequency and using periodic sampling. This single-stage approach with optimized parameters provides the same ripple reduction as multiple cascaded stages but with much lower complexity.
Solution Approach 2:
The patent extracts the essential filtering function from a multi-stage cascaded filter structure and implements it in a single stage enhanced with periodic sampling. By taking out only the necessary filtering capability and achieving it through parameter optimization and temporal sampling, the system avoids the complexity of multiple cascaded filter stages while maintaining effective voltage ripple reduction.
3Object-generated harmful factors
If the cut off frequency is lowered to reduce ripple, then attenuation is improved, but the RC product increases requiring larger components
Solution Approach 1:
The patent fundamentally changes the frequency parameter relationship by operating the low pass filter at a higher cut off frequency (1/8 to 1/4 of PWM frequency) compared to traditional designs. This parameter inversion allows using smaller RC products while achieving acceptable ripple reduction through the combination of higher frequency operation and periodic sampling, directly addressing the issue of large component sizes.
Solution Approach 2:
By introducing periodic sampling at specific phases of the PWM cycle, the patent achieves effective ripple reduction without relying on very low cut off frequencies. This temporal averaging through periodic sampling allows the use of smaller RC components (lower component size) while still achieving the desired attenuation of voltage ripple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively removes voltage ripple and reduces device area, achieving a 'flat' output voltage with improved phase shift, outperforming prior art systems in terms of ripple reduction and phase accuracy.
Implementation Method 1
a low pass filter (LPF), connected to a buffer output, configured to remove a voltage ripple on an LPF output
Implementation Method 2
a first switched capacitor (SC) circuit, connected to the LPF output, configured to remove a remaining voltage ripple
Data Source
AI summary
A voltage proportional to a pulse width modulation (PWM) duty cycle is generated, using a low pass filter (LPF). A 2nd or higher order LPF is provided, giving a 90×(2n+1) degree phase shift for (n=0, 1, 2, . . . ), so that the sampling timing at the latter stages can be at the rising and/or falling edge of the PWM input signal. A switched capacitor circuit after the 2nd or higher order LPF is provided, removing a voltage ripple on an LPF output, and using a smaller device area.