PWM Timer Soft Synchronization for Interlaced Phase Outputs
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Solution Overview
Problem
Existing pulse width modulation systems in rail-bound vehicles face challenges with hard synchronization, requiring control boards to restart in a specific order and limiting independent interrupt handling, which complicates the synchronization of timers and interlacing of PWM outputs.
Innovation Solution
Implementing a soft synchronization method where slave control boards resynchronize their clock rates and timer offsets with a master control board independently of interrupt handling, allowing for flexible interlacing of PWM outputs without requiring synchronized timer changes during restarts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard synchronization is applied to keep clock rate and timer values of control boards the same, then synchronization of timers is achieved, but control boards must be restarted in a specific order and interrupt handling becomes complex
Solution Approach 1:
The patent segments the synchronization function into two independent parts: timer value synchronization and interrupt handling. Each control board maintains its own interrupt handling independently while synchronizing only the timer values through communication bus exchanges. This allows boards to be restarted in any order without affecting the synchronization of timer values across the system.
Solution Approach 2:
The patent extracts the timer synchronization function from the interrupt handling process. By separating these two functions, the timer values can be synchronized through message passing on the communication bus without requiring coordinated interrupt handling or specific restart sequences. The timer synchronization operates independently from the interrupt service routines.
2Manufacturing precision
If timer values are changed to achieve synchronization, then timing alignment is improved, but interrupt handling process becomes dependent and more complex
Solution Approach 1:
The patent segments timing alignment and interrupt handling into separate operational domains. Timer values are synchronized through independent message exchange on the communication bus, while interrupt handling continues to operate autonomously on each control board. This eliminates the coupling between timing synchronization and interrupt processing that exists in hard synchronization systems.
Solution Approach 2:
The patent introduces communication bus message passing as an intermediary mechanism for timer synchronization. Instead of directly coupling timer changes with interrupt handling, the system uses asynchronous messages to convey timer value information between control boards. This intermediary layer decouples the timing synchronization from the interrupt handling process.
3Productivity
If master control board is restarted, then system reinitialization is achieved, but slave boards must wait and synchronization is disrupted
Solution Approach 1:
The patent implements preliminary timer synchronization before restart operations. Each control board continuously maintains synchronized timer values through periodic message exchange on the communication bus. When the master board restarts, slave boards already have up-to-date timer information and can continue operating without waiting for re-synchronization, eliminating downtime.
Solution Approach 2:
The patent ensures continuous timer synchronization through asynchronous message passing that operates independently of board operational state. Even when the master board is restarting, slave boards continue to receive timer synchronization messages or can operate with previously received timing information, maintaining continuous useful action without interruption.
Data Source
AI summary
A pulse width modulation system including a plurality of module building blocks. A master control board includes a master board timer to generate a clock signal having a master timer rate. Each of slave control boards includes a slave board timer and is configured to determine a fictive master board timer based upon timer information received from the master control board via a communication bus, and further to synchronize the timer rate of the slave board timer to the master timer rate. The timer information includes timer offset information defining a time offset between the master board timer and the slave board timer The slave control board applies the time offset in control of pulse width modulated phase outputs such that the position of a slave pulse width modulated phase output signal is controlled in relation to the fictive master board timer.