Quick Error Detection Test Program Insertion for Logic Device Verification

The patent applies preliminary action by inserting check instructions at strategic locations within the test program before errors can propagate through many instructions. These check instructions proactively verify intermediate results and detect errors early in the execution sequence, preventing long error detection latencies that would otherwise occur when errors are only detected at the end of test execution.

The patent uses check instructions as intermediary elements that mediate between the original test instructions and the error detection process. These check instructions serve as intermediate verification points that break down the long error detection latency into smaller segments, allowing errors to be detected closer to their origin without requiring complete test program execution.

The patent applies self-service by enabling automatic generation of test programs with check instructions inserted at strategic locations. The system autonomously analyzes the original test program, identifies appropriate insertion points for check instructions, and generates the enhanced test program without requiring manual intervention, thereby significantly improving productivity while reducing the time and cost associated with manual test program creation.

The patent extracts the labor-intensive manual test program creation process and replaces it with an automated system. By taking out the manual authoring, analysis, and optimization tasks from the human operator, the system achieves rapid generation of optimized test programs with properly placed check instructions, eliminating the time and cost overhead of manual processes.