Quad Flat Non-Leaded Package Thickness Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing manufacturing methods for quad flat non-leaded packages face challenges in reducing package thickness and achieving low manufacturing costs while maintaining efficient signal transmission and chip protection.
Innovation Solution
The method involves using a sacrificed layer, release films, and metal layers to form patterned conductive layers, bonding wires, and encapsulating molding compounds, with the release films allowing for efficient separation of metal layers and reduced package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional manufacturing methods are used for quad flat non-leaded packages, then the package structure is simple and manufacturing process is straightforward, but the package thickness cannot be reduced and manufacturing cost is high
Solution Approach 1:
The patent applies preliminary action by pre-forming patterned conductive layers on sacrificial substrates before chip mounting. The conductive layers are patterned and positioned in advance on the sacrificial substrates, which are then stacked and processed together. This preliminary preparation enables subsequent thinning operations to reduce package thickness while maintaining proper electrical connections, resolving the contradiction between reduced thickness and manufacturing complexity.
Solution Approach 2:
The manufacturing process is segmented into distinct stages: forming patterned conductive layers on separate sacrificial substrates, stacking the substrates with chips, removing sacrificial materials, and final encapsulation. This segmentation allows each step to be optimized independently, enabling thickness reduction through selective material removal while keeping the overall process manageable through systematic division of operations.
2Length of stationary object
If package thickness is reduced, then the package size is minimized and integration is improved, but manufacturing cost increases due to additional process steps
Solution Approach 1:
The patent merges multiple operations into unified process steps. Patterned conductive layers are formed on sacrificial substrates that also provide mechanical support and alignment features, combining structural and electrical functions. The stacking process simultaneously positions multiple chips and conductive layers, and subsequent processing steps handle multiple layers together. This merging reduces the number of separate manufacturing steps required, lowering manufacturing cost while achieving thickness reduction.
Solution Approach 2:
The patent uses sacrificial substrates and sacrificial materials that are intentionally designed to be temporary and inexpensive. These sacrificial elements provide necessary support during manufacturing but are completely removed after serving their purpose. Using cheap, disposable sacrificial materials eliminates the need for expensive permanent structural supports, reducing overall manufacturing cost while enabling the thickness reduction process.
3Speed
If conventional encapsulation methods are used, then chip protection is adequate, but signal transmission path is longer and signal transmission speed is slower
Solution Approach 1:
The patent transitions from conventional planar encapsulation to a three-dimensional stacked architecture. Patterned conductive layers are formed on multiple stacked sacrificial substrates, creating vertical interconnections that significantly shorten signal transmission paths. The encapsulation compound is applied after stacking, providing protection while maintaining the compact three-dimensional structure. This dimensional change enables both faster signal transmission and adequate protection by optimizing the spatial arrangement of electrical connections.
Data Source
AI summary
A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.