QFN Lead Frame Vertical I/O Terminal Inspection
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Solution Overview
Problem
The challenge in packaging semiconductor devices is to maintain the integrity of solder connections between I/O terminals and a printed circuit board (PCB), as conventional inspection methods are inadequate for leadless packaged devices, making it difficult to assess solder quality and potentially leading to 'cold joints' that can render devices useless.
Innovation Solution
A method involving a pre-plated and pre-molded lead frame assembly where I/O terminals are electrically connected and exposed for electroplating, allowing for visible inspection of solder quality and ensuring sufficient electrical conductivity and mechanical strength by creating a plated vertical face during the sawing and singulation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging methods are used for leadless devices, then device size is reduced, but solder connection quality cannot be inspected
Solution Approach 1:
The patent extends the I/O terminals from a two-dimensional plane to a three-dimensional structure by forming vertical faces that protrude from the molding compound. This dimensional change allows the solder connection quality to be inspected from the side rather than requiring inspection from the bottom, solving the inspection difficulty while maintaining the compact leadless package design.
Solution Approach 2:
The patent introduces an intermediary structure (the extended vertical face of the I/O terminal) that mediates between the hidden solder joint and the inspection system. By creating a visible extension of the terminal that correlates with the solder connection quality, the intermediary allows indirect inspection of the otherwise hidden joint without requiring complex imaging equipment.
2Difficulty of detecting and measuring
If I/O terminals are extended for inspection, then solder quality becomes visible, but device complexity increases
Solution Approach 1:
The extended vertical face of the I/O terminal serves multiple functions: it provides mechanical support for the solder joint, enables visual inspection of solder quality, and maintains electrical connectivity. By making the terminal structure multi-functional, the patent avoids adding separate inspection components, thereby reducing overall device complexity while achieving inspection capability.
Solution Approach 2:
The patent merges the inspection function with the existing I/O terminal structure rather than adding a separate inspection mechanism. The terminal itself is designed to provide the inspection interface, combining the electrical connection function with the inspection function in a single integrated structure, thus avoiding increased complexity.
3Measurement precision
If connection traces are severed after assembly, then inspection accuracy improves, but manufacturing process becomes more difficult
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: first forming the extended terminal structure with connection traces intact for structural support, then severing the traces after assembly to enable accurate inspection. This segmentation allows each stage to be optimized independently, with the severing step being a simple, standardized operation that does not significantly complicate the overall manufacturing process.
Solution Approach 2:
The patent performs preliminary actions by forming the extended terminal structure and establishing electrical connections before severing the connection traces. This sequence ensures that the terminal has sufficient mechanical strength during assembly, and the severing is performed as a final preparatory step that enables inspection without requiring complex rework or additional manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient inspection of solder quality and ensures reliable solder connections between I/O terminals and the PCB, enhancing the electrical and thermal performance of semiconductor devices by exposing vertical surfaces for electroplating and severing connection traces after assembly.
Implementation Method 1
The I/O terminals are electroplated to form plated vertical and horizontal surfaces
Data Source
AI summary
Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The semiconductor device includes a QFN package (quad-flat-pack no-leads) built-up substrate lead frame having, a sub-structure of I/O terminals and a die attach area, the I/O terminals and die attach area enveloped in a molding compound; the die attach area has exposed areas to facilitate device die attachment thereon and the terminal I/O terminals provide connection to the device die bond pads. I/O terminals are electrically coupled with one another and to the die attach area with connection traces. The coupled I/O terminals and connection traces facilitate electroplating of exposed vertical surfaces of the I/O terminals during assembly, said connection traces being severed after assembly. Molding compound encapsulates the device die on the built-up substrate lead frame. The exposed vertical surfaces of the I/O terminals enhance the solderability of the assembled QFN device during placement onto a printed circuit board.