QFP Package Bypass Capacitance via Nested Dielectric Layer
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Solution Overview
Problem
Conventional quad flat pack (QFP) packages face issues with voltage drops due to resistance and inductance in the power supply path, which are exacerbated by the location of bypass capacitors outside the package, leading to reduced effectiveness in maintaining stable supply voltage for integrated circuits.
Innovation Solution
A bypass distribution array is integrated within the QFP package, comprising a conductive layer and a dielectric layer between the integrated circuit die and a grounded die paddle, forming a bypass capacitor that provides low-inductance, low-resistance power routing and reduces voltage drops by distributing chip voltages efficiently through short bond wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bypass capacitors are located outside the QFP package on a printed circuit board, then the package structure remains simple and compact, but the inductance and resistance of the supply path reduce the effectiveness of the bypass capacitors in preventing voltage drops
Solution Approach 1:
The bypass capacitor is nested within the QFP package structure, specifically formed between the conductive die paddle and the first conductive layer. This nesting approach allows the capacitor to be integrated into the existing package without adding external components, thereby reducing supply path inductance and resistance while maintaining package compactness.
Solution Approach 2:
The bypass capacitor function is merged with the existing package structures (die paddle and conductive layers) rather than being a separate external component. The die paddle serves as one electrode, the first conductive layer serves as the other electrode, and the dielectric layer between them forms the capacitor, combining multiple functions into a unified structure.
2Reliability
If discrete bypass capacitors are located within the QFP package, then the supply path inductance and resistance are reduced, but the capacitors are bulky and difficult to interconnect
Solution Approach 1:
The invention changes the physical parameters of the capacitor by forming it as a thin-film structure between existing conductive layers rather than using discrete bulky capacitors. The capacitor is formed with minimal thickness and integrated dimensions, transforming it from a large external component to a compact internal structure that is easy to interconnect with the IC die.
3Device complexity
If the power supply path is made longer to connect external bypass capacitors, then the package assembly is simpler, but the resistance and inductance associated with the path increase causing voltage drops
Solution Approach 1:
The bypass capacitor is extracted from its conventional external location on the printed circuit board and repositioned directly within the QFP package adjacent to the IC die. This extraction eliminates the long external supply path and its associated inductance and resistance, creating a short low-impedance path while maintaining simple package assembly through integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes voltage drops and enhances power routing by providing bypass capacitance close to the IC, reducing the impact of inductance and resistance in the power supply path, thus maintaining stable supply voltages and improving the performance of digital logic elements.
Implementation Method 1
the first conductive layer, the first dielectric layer, and the conductive die paddle provide bypass capacitance for the first voltage
Data Source
AI summary
An integrated circuit packaging apparatus includes a first conductive layer disposed between an integrated circuit die and a conductive die paddle. Bond wires connect the first conductive layer to the lead frame package and to the integrated circuit die. A first dielectric layer is disposed between the first conductive layer and the conductive die paddle such that the first conductive layer, the first dielectric layer, and the conductive die paddle provide bypass capacitance. A method for providing bypass capacitance and power routing for an integrated circuit packaging apparatus includes; depositing a first dielectric layer on a conductive die paddle, depositing a first conductive layer on the first dielectric layer, and connecting the first conductive layer to the lead frame package and to the integrated circuit die. The first conductive layer, the first dielectric layer, and the conductive die paddle cooperate to provide bypass capacitance.