Quadra-Phase Clock Generator Using Delay Circuits for Fast Initialization
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Solution Overview
Problem
Conventional quadra-phase designs for generating clock signals require long initialization times and high power consumption, and often employ clock dividers that result in reduced frequency and increased period for multi-phase output signals.
Innovation Solution
A quadra-phase generator architecture that uses delay circuits to produce quadrature clock signals with minimal initialization time, achieving full input clock frequency and wide operational bandwidth by adjusting the delay Δt to align rising and falling edges of input clock signals, and employing phase mixers to generate 0-degree, 90-degree, 180-degree, and 270-degree phase output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PLL with multiple adjustable delay lines or analog cells is used, then multi-phase output signals can be generated, but initialization time is long and power consumption is high
Solution Approach 1:
The patent applies preliminary action by pre-configuring the delay circuits with fixed delay values that correspond to the required phase shifts (0°, 90°, 180°, 270°). This eliminates the need for runtime adjustment and lengthy initialization sequences, allowing the system to generate accurate multi-phase signals immediately upon clock input.
Solution Approach 2:
The patent segments the phase generation function into separate delay circuits, each dedicated to producing a specific phase output. This segmentation allows each circuit to be independently optimized with fixed delay values, improving phase accuracy while reducing the complexity and initialization time compared to a unified adjustable delay line.
2Measurement precision
If conventional PLL with multiple adjustable delay lines or analog cells is used, then multi-phase output signals can be generated, but power consumption is high
Solution Approach 1:
The patent segments the phase generation function into separate delay circuits, each dedicated to producing a specific phase output. This segmentation allows each circuit to be independently optimized with fixed delay values, improving phase accuracy while reducing the complexity and initialization time compared to a unified adjustable delay line.
Solution Approach 2:
The patent employs simple delay circuit elements that can be implemented with minimal hardware resources compared to complex adjustable delay lines or analog cells. These simple circuits consume less power while achieving the required phase accuracy through their fixed, optimized delay characteristics.
3Measurement precision
If clock divider is used to generate multi-phase signals, then phase offset of 90 degrees can be achieved, but output frequency is halved and period is doubled
Solution Approach 1:
The patent introduces delay circuits as intermediary elements between the input clock and the output phases. These delay circuits selectively delay the clock signal by specific amounts to produce the required phase offsets (0°, 90°, 180°, 270°) without altering the fundamental frequency, thus maintaining full output frequency while achieving precise phase relationships.
Solution Approach 2:
The patent changes the delay parameter of the delay circuits to achieve different phase outputs. By adjusting the delay value in each circuit, the system can generate multiple phase outputs with 90-degree offsets while maintaining the full input clock frequency, avoiding the frequency halving effect of clock dividers.
Data Source
AI summary
Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is provided communicatively coupled to the first delay circuit and configured to receive the first delayed clock signal at a first input and a second input clock signal at a second input. The first phase mixer may then generate a first output clock signal at a first output node responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal.