Quadrature Clock Generator Using Sine-Shaping and Polyphase Filters
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Solution Overview
Problem
Existing clock and data recovery (CDR) systems face challenges in generating quadrature clock signals efficiently, particularly at high data rates, as they require complex and power-consuming frequency synthesizers and quadrature dividers, which can lead to interference issues in applications like radio transceivers.
Innovation Solution
A quadrature clock signal generator is developed using a sine-shaping filter and a polyphase filter to generate sinusoidal clock signals, which are then converted into in-phase and quadrature-phase clock signals with a quadrature phase relationship, eliminating the need for frequency synthesizers and quadrature dividers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a frequency synthesizer and quadrature divider are used to generate quadrature clock signals, then the clock signal generation is reliable, but the device complexity and power consumption increase
Solution Approach 1:
The patent combines the functions of frequency synthesis and quadrature division into a single integrated circuit block that generates quadrature clock signals directly from a reference clock. This merging eliminates the need for separate synthesizer and quadrature divider components, thereby reducing device complexity while maintaining reliable quadrature clock signal generation.
Solution Approach 2:
The integrated circuit performs multiple functions simultaneously: it acts as both a frequency synthesizer and a quadrature divider, generating in-phase and quadrature-phase clock signals from a single reference input. This multi-functionality reduces the overall number of components needed in the system.
2Reliability
If a frequency synthesizer and quadrature divider are used to generate quadrature clock signals, then the clock signal generation is reliable, but the power consumption increases
Solution Approach 1:
By merging the synthesizer and quadrator divider into one integrated circuit, the patent eliminates redundant circuitry and reduces overall power consumption while maintaining reliable quadrature clock signal generation.
3Reliability
If a frequency synthesizer and quadrature divider are used to generate quadrature clock signals, then the clock signal generation is reliable, but the die area increases
Solution Approach 1:
The patent integrates the synthesizer and quadrature divider functions into a single compact circuit block, significantly reducing the die area required for clock signal generation while maintaining reliable operation.
4Productivity
If a high speed clock signal is used in radio transceiver applications, then the data transmission rate is high, but interference and coupling increase
Solution Approach 1:
The patent extracts only the necessary quadrature clock signals directly from the reference clock without generating unnecessary high-speed intermediate signals. By eliminating the synthesizer stage that generates high-speed clock signals, the system achieves high data transmission rates while minimizing coupling and interference in radio transceiver applications.
Data Source
AI summary
Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.