Quadrature Delay Clock Generation for 40-50 GHz PLLs
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Solution Overview
Problem
Phased lock loop (PLL) systems face challenges in operating a voltage-controlled oscillator (VCO) at frequencies above 34 GHz due to noise, parasitic capacitance, and narrow tuning range, limiting data rates to 136 Gbps, making it difficult to achieve higher frequency operation and data rates such as 200 Gbps.
Innovation Solution
The implementation of a buffer chain circuit with pairs of in-phase and quadrature inverters, along with phase delay circuits, and a phase detector using PMOS transistors with gates tied to ground, allows the VCO to operate at 40-50 GHz, enabling data rates of 160-200 Gbps and providing a 20% frequency tuning range while saving energy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional PLL circuitry is used with standard inverter designs, then the system can operate reliably, but the VCO frequency is limited to below 34 GHz and data rate is limited to 136 Gbps due to noise, parasitic capacitance, and narrow tuning range
Solution Approach 1:
The patent applies local quality by using different inverter designs for different functional requirements: standard inverters for general buffering and enhanced inverters with specific transistor sizing and coupling for critical phase detection paths. The phase detector uses transistors with gates tied to ground for optimized performance at high frequencies, while buffer chains use tailored inverter pairs to minimize parasitic effects locally where they impact signal integrity most.
Solution Approach 2:
The patent implements dynamics through voltage-controlled tuning of the VCO frequency range from 40-50 GHz, allowing the system to adapt its operating frequency dynamically. The phase detector and buffer chains are designed to maintain performance across this dynamic frequency range, enabling data rates from 160-200 Gbps while preserving signal integrity through adaptive circuit behavior.
2Productivity
If the VCO operating frequency is increased above 34 GHz to achieve higher data rates, then data rate can exceed 136 Gbps, but noise, parasitic capacitance, and narrow tuning range make operation difficult
Solution Approach 1:
The patent applies parameter changes by systematically adjusting transistor dimensions, coupling capacitances, and bias conditions to optimize circuit performance at 40-50 GHz operation. The inverter pairs use specific transistor width-to-length ratios and coupling capacitor values to minimize parasitic effects and maintain signal integrity at high frequencies, enabling 160-200 Gbps data rates while managing the increased design complexity through parameter optimization.
3Speed
If buffer chain circuitry with phase delay circuits is added to enable high-frequency operation, then VCO can operate at 40-50 GHz, but the circuit complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the buffer chain into multiple inverter pairs with specific phase delay characteristics. Each inverter pair is designed to contribute a controlled phase shift, allowing the overall buffer chain to achieve the required phase relationships for quadrature clock generation at 40-50 GHz. This segmented approach manages complexity by breaking down the overall buffering function into manageable, repeatable units with predictable behavior.
Data Source
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AI summary
A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.