Quadrature Phase Detection Circuit for Low-Jitter Zero Crossing
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Solution Overview
Problem
Conventional zero phase detectors in high-speed data transmission systems are limited by complex circuit architectures, high power consumption, and significant jitter in output clock signals, making them unsuitable for modern high-speed applications.
Innovation Solution
A high-speed phase detection circuit using two quadrature phase detectors and delay circuits to generate a zero output when input signals are aligned, with a subtraction circuit to cancel out variations and achieve zero phase detection without precise delays, reducing power consumption and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional zero phase detectors are used in high-speed data transmission systems, then phase detection function is provided, but power consumption is high and circuit architecture is complex
Solution Approach 1:
The phase detector is divided into two separate quadrature phase detectors, each handling a specific quadrant of phase detection. This segmentation allows each detector to be optimized for its specific function, reducing the overall complexity and power consumption compared to a single conventional zero phase detector that must handle all cases.
Solution Approach 2:
The invention transitions from traditional time-domain phase detection to a complex plane representation where phase detection is performed in the I-Q (in-phase and quadrature) domain. This dimensional transformation enables more efficient phase comparison and reduces the computational complexity required for high-speed operation.
2Reliability
If conventional zero phase detectors are used, then phase alignment is achieved, but jitter in output clock signal is significant
Solution Approach 1:
The invention implements a feedback mechanism where the outputs of the two quadrature phase detectors are combined and fed back to control the phase alignment. This feedback loop continuously adjusts the phase relationship between input signals, reducing jitter in the output clock signal while maintaining accurate phase alignment.
Solution Approach 2:
The system dynamically adjusts the phase difference parameter between the two quadrature phase detectors based on the detected phase relationship. By changing this parameter adaptively, the system optimizes both jitter reduction and phase alignment accuracy for different operating conditions.
3Speed
If high-speed reference clock frequency is divided by input frequency divider circuit, then lower speed clock signal is generated, but power consumption is significant and jitter is generated
Solution Approach 1:
The invention extracts and eliminates the need for the input frequency divider circuit by using the phase detection mechanism to directly generate the required clock signals at the appropriate speeds. This removal of the frequency divider eliminates its power consumption and jitter generation while maintaining the necessary clock signal speeds.
4Productivity
If XOR based quadrature phase detector is used, then high speed operation is achieved, but zero output is generated when signals are 90 degrees out of phase
Solution Approach 1:
The invention combines two quadrature phase detectors with complementary characteristics to create a complete phase detection system. While each individual detector has limited detection range, their combination covers the full 360-degree phase range with high speed operation, and their outputs are merged to provide accurate phase detection in all quadrants.
Data Source
AI summary
A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.