Quadrilateral Epitaxial Source/Drain Layers for Low-Leakage GAA Transistors

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, challenges arise in reducing feature sizes while maintaining effective integration density, leading to issues such as increased leakage and Drain-Induced-Barrier-Lowering (DIBL) in Gate-All-Around (GAA) transistors.

Innovation Solution

The formation of GAA transistors using a {110} substrate with epitaxy source/drain regions shaped as quadrilaterals, specifically rectangles or trapezoids, to ensure uniform thickness and reduce junction leakage, employing controlled epitaxy processes to form layers with controlled dopant concentrations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional epitaxy source/drain regions with triangular layers are used, then the fabrication process is simpler, but junction leakage and DIBL increase due to non-uniform thickness

Engineering Contradiction:
Improvejunction leakageVSAvoidepitaxy process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source/drain region is divided into multiple epitaxial layers with different orientations. The first epitaxial layer has a first orientation and the second epitaxial layer has a second orientation different from the first, creating a segmented structure that achieves uniform thickness profile and reduces junction leakage while managing process complexity through systematic layering

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The source/drain region employs a composite structure combining multiple epitaxial layers with different crystallographic orientations. This composite approach leverages the beneficial properties of each orientation to achieve overall uniform thickness and improved electrical characteristics, balancing reliability enhancement with manageable fabrication complexity

Inventive Principle:
Principle #40Composite materials

2Productivity

If feature sizes are reduced to increase integration density, then more components can be integrated, but leakage and DIBL worsen

Engineering Contradiction:
Improveintegration densityVSAvoidleakage
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by creating regions with different epitaxial layer orientations at specific locations within the source/drain structure. This local differentiation ensures uniform thickness in critical areas to reduce leakage while maintaining overall device scaling for high integration density

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention changes the crystallographic orientation parameter of epitaxial layers to achieve uniform thickness profiles. By adjusting the orientation angles and sequence of deposition, the patent optimizes the thickness uniformity to reduce leakage and DIBL effects while maintaining scaled dimensions for high integration density

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces junction leakage and minimizes Drain-Induced-Barrier-Lowering (DIBL) by ensuring uniform thickness and controlled dopant distribution in the source/drain regions, enhancing transistor performance.

Implementation Method 1

forming a first source/drain region comprising growing first epitaxial layers in the source/drain recess, wherein the first epitaxial layers are grown on sidewalls of the plurality of nanostructures

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20250294805A1Method of forming source/drain regions with quadrilateral layers
Publication Date: 2025.09.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250294805A1 patent drawing
  • US20250294805A1 patent drawing
  • US20250294805A1 patent drawing

AI summary

A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.