Quantum Signal Carrier Chip With Low-Loss Silicon Capping
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Solution Overview
Problem
Existing quantum computing systems face challenges in maintaining high quality factor (Q) and long qubit coherence time due to interference from qubit control and readout circuits, as well as lossy dielectrics, which limit the scalability and efficiency of signal distribution.
Innovation Solution
A multilayer wiring stack with a low-loss capping layer formed from single crystal silicon is used to house qubit control and readout elements, connected via conductive vias to the wiring stack, allowing these elements to be positioned separately from the qubits, reducing interference and enabling scalable signal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If qubit control and readout circuits are integrated closely with qubits, then device complexity is reduced, but quality factor and coherence time deteriorate due to interference and lossy dielectrics
Solution Approach 1:
The device is divided into two separate chips: a first chip containing qubits and a second chip containing control and readout circuits. This segmentation allows each component to be optimized independently, placing lossy dielectrics only where needed for signal distribution while keeping qubit environments clean for high coherence
Solution Approach 2:
A multilayer wiring stack with low-loss dielectric material acts as an intermediary between the qubit chip and control circuits. This intermediate structure enables signal distribution while minimizing interference and energy loss, bridging the gap between integrated control and high-quality factor requirements
2Ease of manufacture
If traditional dielectric materials are used in wiring stacks, then manufacturing is easier, but signal loss increases reducing quality factor
Solution Approach 1:
The dielectric material parameters are changed from traditional lossy materials to low-loss materials with specific properties (tan δ < 0.001). This parameter change reduces signal loss and increases quality factor while maintaining compatibility with standard semiconductor fabrication processes
Solution Approach 2:
A composite multilayer wiring stack is used, combining multiple dielectric layers with different properties. The stack includes low-loss dielectric material for signal distribution layers and can incorporate metal carrier bonding layers and metal capping bonding layers, creating a composite structure that optimizes both manufacturing and performance
3Device complexity
If control circuits are positioned close to qubits, then signal distribution is simpler, but interference from circuits increases reducing coherence time
Solution Approach 1:
Separating control circuits from qubits into different chips eliminates direct interference while the multilayer wiring stack provides organized signal distribution pathways. This segmentation maintains signal distribution capability through structured interconnects while removing harmful electromagnetic interference from the qubit environment
Solution Approach 2:
The low-loss dielectric wiring stack serves as an intermediary transmission medium between distant control circuits and qubits. This intermediate structure enables long-distance signal distribution with minimal loss and interference, replacing direct proximity coupling with mediated coupling through optimized transmission lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains high Q and coherence time for qubit control and readout elements, enhances signal distribution, and allows for increased scalability of quantum computing devices by positioning these elements on a low-loss dielectric layer, thereby reducing interference and maintaining high quality factor.
Implementation Method 1
the capping layer comprises a single crystal silicon dielectric layer
Implementation Method 2
forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer
Data Source
AI summary
A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.