Quantum Dot Memory Switch for FPGA Area and Voltage Reduction
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) face challenges due to the large area occupancy of pass transistors and static random access memory (SRAM) cells used as binary memory wiring switches, which limits spatial efficiency and requires high programming and operation voltages.
Innovation Solution
A field-effect quantum dot memory switch device is developed, featuring a channel region with doped source and drain regions, a charge storage region with quantum structures or deep traps, and a gate dielectric layer, allowing for low-voltage programming and operation by injecting and retaining carriers in quantum structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a pass transistor and SRAM cell are used as binary memory wiring switch in FPGAs, then the device can be reprogrammed subsequent to manufacture, but the area taken by the pass transistor and SRAM cell is a large fraction of the total area inside FPGA
Solution Approach 1:
The patent combines the pass transistor and memory cell into a single quantum dot memory switch device. The quantum dot structure integrates the switching function ( traditionally requiring a pass transistor) and the memory storage function (traditionally requiring an SRAM cell) into one compact device, thereby reducing area occupancy while maintaining reprogrammability.
Solution Approach 2:
The patent changes the fundamental operating parameters from conventional transistor-based switching to quantum dot-based carrier injection and retention. By using quantum confinement effects and carrier trapping in quantum dots, the device achieves memory functionality with different physical mechanisms that require less area compared to traditional SRAM cells.
2Reliability
If conventional pass transistor and SRAM cell are used, then binary memory switching function is achieved, but high programming and operation voltages are required
Solution Approach 1:
The patent replaces the conventional transistor-based electrical switching mechanism with a quantum mechanical carrier injection mechanism. Instead of using high voltages to control current flow through transistors, the device uses lower voltages to inject carriers into quantum dots, where quantum confinement effects retain the carriers, achieving memory switching with reduced energy consumption.
Solution Approach 2:
The patent utilizes phase transitions in the form of carrier injection and retention in quantum dots. By controlling the injection of carriers into the quantum dot structure and their subsequent retention or removal, the device achieves binary memory switching functionality with lower voltages compared to conventional transistor switching.
3Reliability
If conventional memory cell structure is used, then memory storage is achieved, but spatial efficiency is limited
Solution Approach 1:
The patent segments the memory storage function into discrete quantum dot structures that can be independently controlled. Each quantum dot acts as an independent storage element, allowing for high-density integration and improved spatial efficiency compared to conventional memory cell structures that require multiple transistors per storage element.
Solution Approach 2:
The patent transitions from planar transistor-based memory cells to vertically structured quantum dot memory switches. The quantum dots are positioned in a charge storage region between the gate and channel region, utilizing the vertical dimension to achieve compact integration and improved spatial efficiency while maintaining memory storage functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a dense binary memory switch with combined pass transistor and memory cell functions, achieving low programming and operation voltages, improved spatial efficiency, and applicability to FPGAs, while maintaining effective carrier retention.
Implementation Method 1
a charge storage region including a semiconductor layer containing quantum structures, deep traps or combinations thereof
Implementation Method 2
causing the carriers to be retained by the quantum structures, deep traps or combinations thereof
Data Source
AI summary
A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and directly contacting a channel region. The charge storage region contains quantum structures, deep traps or combinations thereof and is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.