Quasi-Monolithic Chip Layers for High-Density Die Interconnects
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Solution Overview
Problem
Current IC packaging technologies face limitations in achieving high interconnect density, scalability, and yield due to the use of solder-based connectivity, which results in increased power consumption, higher costs, and manufacturing constraints, especially when integrating large circuitry sizes that exceed reticle limits and require uniform manufacturing processes for all dies on a wafer.
Innovation Solution
The implementation of a quasi-monolithic chip layer architecture with interconnects having a pitch of less than 10 micrometers between adjacent interconnects, coupled with a package substrate, allows for monolithic performance and disaggregation flexibility, enabling high-density interconnects and scalable solutions for wafer-level supercomputers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder-based connectivity is used in current IC packaging, then electrical connections between dies are established, but power consumption increases and manufacturing flexibility decreases
Solution Approach 1:
The patent extracts and eliminates the solder material from the interconnect structure, replacing it with direct metal-to-metal bonding between dies. This removes the harmful factor (solder) that causes high power consumption and manufacturing constraints, while maintaining reliable electrical connections through alternative bonding mechanisms
Solution Approach 2:
The patent changes the physical and chemical parameters of the interconnect interface by transitioning from solder-based connections to direct metal bonding. This involves modifying the bonding surface properties, temperature profiles, and material compositions to achieve reliable connections without solder, thereby reducing power consumption and improving manufacturing flexibility
2Reliability
If solder-based connectivity is used in current IC packaging, then electrical connections are established, but manufacturing constraints and costs increase
Solution Approach 1:
The patent removes solder from the packaging process, eliminating the associated manufacturing constraints such as reflow oven requirements, solder paste application steps, and strict humidity/temperature controls during assembly. This enables more flexible and cost-effective manufacturing processes
Solution Approach 2:
The patent enables independent fabrication and testing of individual dies before final assembly, as the direct bonding interface allows for better yield management. Dies can be manufactured separately on different wafers, tested individually, and then bonded together, providing manufacturing flexibility that solder-based approaches cannot achieve
3Adaptability or versatility
If large circuitry sizes exceeding reticle limits are integrated, then functional capabilities are enhanced, but uniform manufacturing processes cannot be applied
Solution Approach 1:
The patent divides large-scale circuitry into multiple smaller die segments that can each be manufactured using standard reticle processes with uniform precision. These segmented dies are then bonded together to form the complete large-scale functional system, achieving both large circuitry capability and manufacturing uniformity
Solution Approach 2:
The patent transitions from planar integration (single reticle) to three-dimensional stacking of multiple dies. By moving to the vertical dimension through advanced packaging, the system achieves large equivalent circuitry area while each individual die maintains standard manufacturing dimensions and precision
4Productivity
If interconnect density is increased, then data movement efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces traditional mechanical alignment methods with direct metal-to-metal bonding mechanisms that provide self-alignment and inherent precision. The bonding process itself creates the precise interconnect positions, eliminating the need for separate alignment steps and reducing the overall manufacturing precision burden
Data Source
AI summary
Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies, adjacent layers in the plurality of layers being coupled together by first interconnects and a package substrate coupled to the plurality of layers by second interconnects. A first layer in the plurality of layers comprises a dielectric material surrounding a first IC die in the first layer, a second layer in the plurality of layers is adjacent and non-coplanar with the first layer, the second layer comprises a first circuit region and a second circuit region separated by a third circuit region, the first circuit region and the second circuit region are bounded by respective guard rings, and the first IC die comprises conductive pathways conductively coupling conductive traces in the first circuit region with conductive traces in the second circuit region.