Quasi-Volatile Memory Module With 3D NOR Arrays

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Solution Overview

Problem

Conventional DRAM technology faces limitations in density improvement due to increased power consumption and heat dissipation as refresh rates increase, necessitating a new memory type with higher density and lower refresh requirements.

Innovation Solution

A quasi-volatile memory system utilizing 3-dimensional arrays of NOR-type memory strings formed over a semiconductor substrate, which offers longer data retention and lower refresh rates, integrated with a memory controller circuit for efficient operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If DRAM capacitor size is reduced to increase density, then data density is improved, but refresh rate must increase which worsens power consumption

Engineering Contradiction:
Improvedata densityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent transitions from volatile DRAM to quasi-volatile memory by changing the fundamental retention mechanism from capacitor charge to magnetic domain states. This parameter change enables data retention without continuous refreshing, eliminating the need for high refresh rates even as density increases through capacitor size reduction.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces a new dimension of memory organization using three-dimensional arrays of memory strings with magnetic tunnel junctions. This dimensional change allows for higher density storage while maintaining low power consumption through the inherent non-volatility of magnetic storage, bypassing the DRAM refresh paradigm entirely.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Duration of action of stationary object

If DRAM refresh rate is increased to maintain data with smaller capacitors, then data retention is improved, but power consumption and heat dissipation worsen

Engineering Contradiction:
Improvedata retentionVSAvoidpower consumption
Core Design Contradiction:
Duration of action of stationary objectVSUse of energy by stationary object

Solution Approach 1:

The quasi-volatile memory system provides self-service data retention through magnetic domain stability. The magnetic tunnel junctions inherently maintain their state without external intervention, eliminating the need for active refresh operations and their associated power consumption and heat generation.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent eliminates periodic refresh actions entirely by using magnetic storage that maintains data retention without time-limited charge storage. The magnetic domains remain stable indefinitely without requiring periodic rewriting or refreshing operations.

Inventive Principle:
Principle #19Periodic action

3Duration of action of stationary object

If more memory units are refreshed in each refresh cycle to maintain conventional refresh rate, then data retention is improved, but power consumption and heat dissipation worsen

Engineering Contradiction:
Improvedata retentionVSAvoidheat dissipation
Core Design Contradiction:
Duration of action of stationary objectVSLoss of energy

Solution Approach 1:

Each memory string in the quasi-volatile system serves itself by maintaining data through stable magnetic domains. No external refresh operations are needed, eliminating the energy loss and heat dissipation associated with refreshing multiple memory units in each cycle.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11508693B2High capacity memory module including wafer-section memory circuit
Publication Date: 2022.11.22 SUNRISE MEMORY CORP
  • US11508693B2 patent drawing
  • US11508693B2 patent drawing
  • US11508693B2 patent drawing

AI summary

A memory device includes a first semiconductor wafer portion including two or more adjacent quasi-volatile memory circuits formed on a common semiconductor substrate where each quasi-volatile memory circuit being isolated from an adjacent quasi-volatile memory circuit by scribe lines; and a second semiconductor wafer portion including at least one memory controller circuit formed on a semiconductor substrate. The memory controller circuit includes logic circuits and interface circuits. The memory controller circuit is interconnected to the two or more adjacent quasi-volatile memory circuits of the first semiconductor wafer portion through interconnect structures and the memory controller circuit operates the two or more quasi-volatile memory circuits as one or more quasi-volatile memories.