Race Logic Synthesis for IC Design Verification
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Solution Overview
Problem
The increasing complexity and density of large-scale IC designs lead to significant challenges in functional verification, with race logic issues causing inconsistent analysis results across different CPU environments and potentially leading to intermittent failures in IC chips. Existing solutions fail to effectively detect and eliminate race logic, especially when it is present in third-party IP blocks.
Innovation Solution
A set of race logic synthesis technologies that re-synthesize and eliminate race logic in compiled IC design databases, allowing for consistent verification across single- or multi-CPU environments by replacing behavioral/RTL logic with race-free equivalents, which can be incorporated into various EDA tools such as HDL/ESL logic simulators, fault simulators, and static timing analyzers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multithreaded/multi-CPU EDA verification tools are used to accelerate verification, then verification time is reduced significantly, but race logic issues cause inconsistent analysis results across different CPU environments
Solution Approach 1:
The system performs preliminary detection of race logic conditions during the verification process by monitoring for simultaneous assignments to the same signal. This preliminary action identifies potential race conditions before they cause inconsistent results, allowing the system to resolve them and ensure consistent analysis across single-CPU and multi-CPU environments.
2Loss of time
If third-party IP blocks are reused to speed up development, then development time is reduced, but race logic in these IP blocks cannot be fixed by IC designers
Solution Approach 1:
The EDA tool acts as an intermediary between the third-party IP block and the IC designer. It detects race logic conditions within the IP block and provides synthesized, race-free versions of the IP block or generates modification suggestions, enabling designers to fix race conditions in IP blocks without direct access to the original IP source code.
Solution Approach 2:
The system creates synthesized copies of the IP block logic that eliminate race conditions. By generating alternative implementations of the same functional behavior without race logic, the system preserves the functionality of third-party IP while removing the harmful race conditions that prevent fixing.
3Device complexity
If race logic is not detected and eliminated, then verification process remains simple, but IC chips manifest intermittent failures in the field
Solution Approach 1:
The system implements feedback by continuously monitoring verification results for race logic conditions and automatically generating corrected versions of the design. This feedback loop ensures that race conditions are detected and eliminated, preventing intermittent failures in the field while maintaining a manageable verification process through automated detection and correction.
Data Source
AI summary
Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, HDL (hardware description language) and/or ESL (electronic system level) design source files of an IC design are compiled into a common design database. Race logic analysis is performed on the IC design, either by a third-party tool or by the same EDA (electronic design automation) tool that also performing race logic synthesis, if the latter has built-in race logic audit functions. Based on the race logic audit results, race logic synthesis is performed on the common design database, and getting rid of all identified race logic in the IC design. This renders the EDA tool can perform concurrent analysis of the IC design, via the race-free common design database, using multi-CPU/core computers and the results will be the same as if the EDA tool had performed serial analysis of the IC design using a single-CPU/core computer. Another aspect of the invention is outputting the re-synthesized logic in the common design database to new HDL/ESL source files. User may use these revised source files to analyze the IC design using other third-party EDA design/verification tools.