Multi-Module Radar Clock Phase Alignment Using PLL Phase Selection
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Solution Overview
Problem
Existing radar systems with multiple transceiver modules face limitations in spatial and velocity resolution due to phase skew in clock signals, which is challenging to align without expensive design and calibration efforts.
Innovation Solution
A radar system with a leader-follower configuration, where each module includes a phase-locked loop (PLL) clock signal generator with a divide-by-n clock divider and a multiplexer to generate selectable clock phases, allowing for phase coherent sampling clocks across modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a perfectly designed PCB is used to align reference clocks, then clock phase alignment is improved, but manufacturing cost and complexity increase significantly
Solution Approach 1:
The patent introduces delay cells as intermediary components in the clock distribution network. These delay cells act as mediators that can be inserted at strategic points in the PCB trace paths to adjust and equalize the phase of reference clocks reaching different transceiver modules, thereby achieving precise clock alignment without requiring a completely redesigned PCB layout.
Solution Approach 2:
The patent changes the electrical parameters of the clock distribution system by introducing adjustable delay elements. By modifying the propagation delay parameter of clock signals through programmable delay cells, the system can dynamically adjust phase alignment to compensate for PCB trace length variations and manufacturing tolerances, achieving precise synchronization without complex PCB design.
2Measurement precision
If delay lines are used to adjust reference phase in each module, then clock alignment is improved, but phase noise performance deteriorates and area increases
Solution Approach 1:
The patent uses a single high-quality reference oscillator in the leader module to generate the master reference clock. Instead of placing independent oscillators (and their associated phase noise) in each follower module, the system copies the reference clock signal from the leader module and distributes it to all follower modules through the PCB, thereby achieving clock alignment without multiplying phase noise sources.
Solution Approach 2:
The patent merges the reference clock generation function into a single leader module rather than distributing independent oscillators across all modules. By combining the reference clock source into one location and distributing the clock signal to all other modules, the system reduces the total phase noise in the system while still achieving precise clock alignment through centralized control.
3Measurement precision
If delay lines are used to adjust ADC sampling clock, then sampling alignment is improved, but power consumption increases due to higher frequency operation
Solution Approach 1:
The patent implements a feedback mechanism where the leader module monitors the timing of ADC sampling in follower modules and sends correction signals back to adjust the sampling clock phases. This feedback loop enables precise sampling alignment without requiring high-power delay lines in each module, as the adjustments can be made through lower-power digital control signals that modify the timing of existing clock distributions.
4Measurement precision
If manual or automatic phase adjustment is performed to remove production spread, then clock alignment is improved, but manufacturing cost and time increase
Solution Approach 1:
The patent transforms the static PCB trace length compensation approach into a dynamic solution using programmable delay cells. Instead of manually adjusting or fixing trace lengths during manufacturing, the system allows dynamic programming of delay values after assembly, enabling automatic compensation for production variations without requiring precise manual adjustment during the manufacturing process itself.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution simplifies the alignment of clock phases, reduces phase noise, and enables higher resolution in radar systems without the need for complex delay lines or extensive calibration processes.
Implementation Method 1
each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator comprising: a phase comparator connected to receive the first clock signal and a feedback signal; a loop filter connected to receive an output signal from the phase comparator; a second oscillator connected to receive an output signal from the loop filter and generate a second clock signal at a second frequency
Implementation Method 2
a divide by n clock divider connected to receive the second clock signal from the second oscillator and to output 2n phase shifted clock signals at a third frequency
Implementation Method 3
a multiplexer connected to receive the 2n phase shifted clock signals from the divide by n clock divider and output a third clock signal selected by an input phase select signal
Data Source
AI summary
Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system (400) comprising a plurality of radar transceiver modules (401, 402) mounted to a common PCB (404), the plurality of radar transceiver modules comprising a leader module (401) and one or more follower modules (402), the leader module (401) comprising a first oscillator (403) configured to provide a first clock signal at a first frequency to each follower module (402), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (300), the PLL clock signal generator (300) comprising a divide by n clock divider (304) arranged to output 2n phase shifted clock signals (314) at a third frequency and a multiplexer (306) connected to receive the 2n phase shifted clock signals from the divide by n clock divider (304) and output a third clock signal (308) selected by an input phase select signal (307).