Raised Source-Drain Transistor Fabrication for Sharp Junctions
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Solution Overview
Problem
Conventional field effect transistor (FET) device fabrication processes face challenges in achieving high mobility channel regions and sharp junctions between the source-drain and channel regions, particularly as device sizes shrink, leading to issues with diffused junctions, increased resistance, and pitch scaling.
Innovation Solution
The method involves growing alternating semiconductor stress release buffer and defect cap layers, followed by epitaxial growth of defect-free and fully stress-released semiconductor layers, and subsequent doping of indium-phosphorous and indium-gallium-arsenic layers to form a substrate that supports high mobility channel regions and sharp junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional gate-first or gate-last fabrication processes are used, then device fabrication is simplified, but diffused junctions form which degrade short channel control and increase resistance
Solution Approach 1:
The patent forms raised source-drain regions through epitaxial growth before forming the gate structure. This preliminary action allows the junctions to be defined by the epitaxial layer boundaries rather than by subsequent gate masking, achieving sharp junctions without compromising fabrication simplicity. The raised source-drain regions are grown to protrude above the substrate surface, and their lateral extent defines the junction position with high precision.
Solution Approach 2:
The patent segments the source and drain regions into distinct raised portions that protrude above the substrate surface. This segmentation allows independent control of the source and drain junction positions through the epitaxial growth process, enabling sharp junction definition. The raised source-drain regions are formed as separate structures with controlled lateral dimensions, decoupling the junction sharpness from the gate fabrication process.
2Productivity
If device size is scaled down, then device density increases, but diffused junctions worsen short channel control
Solution Approach 1:
By forming raised source-drain regions before gate fabrication, the patent establishes sharp junction boundaries in advance. This preliminary action ensures that even as device dimensions are scaled down, the junction sharpness is maintained by the epitaxial layer boundaries rather than being degraded by subsequent processing steps. The raised regions' lateral extent, defined during epitaxial growth, provides precise junction positioning independent of gate dimensions.
3Ease of manufacture
If conventional epitaxial growth is used after gate formation, then source-drain regions are formed, but junction sharpness is degraded
Solution Approach 1:
The patent inverts the conventional process sequence by forming raised source-drain regions through epitaxial growth before forming the gate structure. This inversion allows the junctions to be defined by the epitaxial layer boundaries rather than by gate masking, achieving sharp junctions. The raised source-drain regions are grown to protrude above the substrate, and their lateral extent defines the junction position with high precision, eliminating the diffused junction problem inherent in conventional sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of transistors with high mobility channel regions and sharp junctions, reducing resistance and improving device performance by controlling dopant diffusion and junction sharpness.
Implementation Method 1
repeating epitaxial processes to grow a first stack of alternating semiconductor stress release buffer and semiconductor defect cap layers
Implementation Method 2
epitaxially growing a defect free and fully stress released semiconductor layer
Implementation Method 3
doping the further indium-gallium-arsenic layer with a Group IV or Group VI dopant
Data Source
AI summary
A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.