RAM Bank Layout for Selective Deep-Sleep Data Retention
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Solution Overview
Problem
Volatile memory devices in low power consumption devices, such as IoT devices, consume significant power during deep sleep mode due to large memory banks that need to remain powered to retain data, necessitating an improved method for memory allocation to minimize power usage.
Innovation Solution
A memory layout is optimized by segregating volatile memory into banks that can be independently powered, with critical data near the start and non-essential data near the end, using a memory manager to allocate 'long-term' and 'short-term' blocks strategically and decoupling memory reservations from retention during deep sleep mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If volatile memory banks are made large to retain critical data during deep sleep mode, then data retention capability is improved, but power consumption increases
Solution Approach 1:
The volatile memory is divided into multiple independently controllable banks. Critical data is placed in specific banks that remain powered during deep sleep mode, while non-critical banks are powered down. This segmentation allows selective retention of only essential data, reducing overall power consumption while maintaining data retention capability for critical information.
Solution Approach 2:
Different regions of memory are assigned different retention characteristics. The memory layout places critical data (secure RAM, instructions, metadata) in banks that remain powered, while non-critical data (buffers) is placed in banks that can be powered down. This local differentiation optimizes the balance between data retention and power consumption.
2Device complexity
If memory banks are made large to reduce the number of banks needed, then device complexity is reduced, but power consumption during deep sleep mode increases
Solution Approach 1:
Rather than using fewer large banks, the system uses multiple smaller banks that can be independently controlled. This allows the device to power down individual banks during deep sleep mode, reducing overall power consumption while maintaining the same total memory capacity. The segmentation enables fine-grained power management.
3Speed
If all memory banks are powered during deep sleep mode, then memory access speed is improved, but power consumption increases
Solution Approach 1:
The memory system is segmented into multiple banks that can be independently powered. During deep sleep mode, only the banks containing critical data remain powered, allowing fast access to essential information while other banks are powered down to reduce consumption. This selective powering strategy optimizes the trade-off between speed and power.
Solution Approach 2:
Critical data is pre-positioned in specific memory banks during the initialization phase. This preliminary action ensures that when deep sleep mode is entered, the system knows exactly which banks to keep powered, enabling fast access to critical data without needing to power all banks.
Data Source
AI summary
An improved layout for volatile memory is disclosed. The volatile memory comprises a plurality of banks that may be independently powered during deep sleep mode. The memory layout attempts to locate all items and data that are retained near one end of the volatile memory, such as near the starting address of the volatile memory. These items include secure RAM, instructions that have been copied from a nonvolatile memory, and metadata associated with memory reservations. Additionally, buffers that do not need to be retained during deep sleep mode are disposed on the opposite end of the volatile memory, such as near the ending address. Memory that is allocated for the user level software is categorized as “long-term” and “short-term”. Allocations of “long-term” blocks are located near the metadata for the memory reservations, while allocations of “short-term” blocks are located near the opposite end of the memory.