Ramped Semiconductor Interconnect for Reliable Multilayer Connections
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Solution Overview
Problem
Existing semiconductor fabrication techniques face challenges with vertical interconnect access (VIA) due to issues such as non-conductive gaps, rough VIA walls, open holes, and mechanical instability, which affect conductivity and stability.
Innovation Solution
Employing additive manufacturing techniques to create a ramped interconnect access (RIA) using conductive inks, such as nanoparticle inks, to connect multilayer circuits through a ramped pathway, allowing for controlled deposition of conductive material via methods like piezo-jet printing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive material is inserted into the VIA to fill the hole, then electrical connection is provided, but the VIA walls being overly rough cause the conductive material to get caught along the side walls, impeding conductivity
Solution Approach 1:
By changing from vertical to ramped geometry, the patent creates a surface that naturally guides conductive material flow. The controlled slope angles (e.g., 30-60 degrees) prevent material from adhering to vertical walls while ensuring complete coverage, eliminating the 'getting caught' problem inherent in rough vertical VIA walls.
Solution Approach 2:
The patent modifies the geometric parameters of the interconnect structure by introducing specific ramp angles and surface profiles. These parameter changes optimize the flow characteristics of conductive material during deposition, ensuring smooth progression along the ramp without adhesion or trapping issues.
2Reliability
If conductive material is inserted into the VIA, then electrical connection is provided, but roughing of the conductive material during insertion creates open holes that adversely affect conductivity
Solution Approach 1:
The ramped surface with optimized curvature radii prevents mechanical stress concentration during conductive material deposition. This smooth, curved geometry eliminates sharp corners and abrupt transitions that would cause material roughing or open hole formation, ensuring continuous, defect-free conductive paths.
Solution Approach 2:
By controlling the ramp angle, surface roughness parameters, and deposition parameters specific to the ramped geometry, the patent prevents material degradation during insertion. The optimized parameters ensure material remains intact and conductive throughout the deposition process.
3Reliability
If a vertical hole is filled with conductive material to provide electrical connection, then conductivity between layers is achieved, but mechanical instability of the conductive material in the hole adversely affects VIA conductivity due to lack of mechanical support
Solution Approach 1:
The ramped interconnect geometry provides inherent mechanical support through its extended lateral profile. The sloped structure distributes mechanical stresses along the length of the conductive material rather than concentrating them in a vertical column, preventing collapse or displacement and ensuring long-term stability of the electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The RIA addresses conductivity and stability issues by providing a reliable electrical connection between circuit layers with improved mechanical support and controlled ink deposition, enhancing the reliability of semiconductor fabrication.
Implementation Method 1
additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component
Data Source
AI summary
The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.